 | 2010 |
| 15 |  | Wangyang Zhang,
Tsung-Hao Chen,
Ming Yuan Ting,
Xin Li:
Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression.
DAC 2010: 897-902 |
| 14 |  | Tsung-Hao Chen,
Cheng-Wu Chen:
Application of data mining to the spatial heterogeneity of foreclosed mortgages.
Expert Syst. Appl. 37(2): 993-997 (2010) |
| 2009 |
| 13 |  | Hong Zhang,
Tsung-Hao Chen,
Ming Yuan Ting,
Xin Li:
Efficient design-specific worst-case corner extraction for integrated circuits.
DAC 2009: 386-389 |
| 2006 |
| 12 |  | Ting-Ya Hsieh,
Morris H. L. Wang,
Cheng-Wu Chen,
Chen-Yuan Chen,
Shang-En Yu,
Hsien-Chueh Yang,
Tsung-Hao Chen:
A New Viewpoint of S-curve Regression Model and its Application to Construction Management.
International Journal on Artificial Intelligence Tools 15(2): 131-142 (2006) |
| 2005 |
| 11 |  | Yu-Min Lee,
Yahong Cao,
Tsung-Hao Chen,
Janet Meiling Wang,
Charlie Chung-Ping Chen:
HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 797-806 (2005) |
| 2004 |
| 10 |  | Clement Luk,
Tsung-Hao Chen,
Charlie Chung-Ping Chen:
Frequency-dependent reluctance extraction.
ASP-DAC 2004: 792-797 |
| 9 |  | Tsung-Hao Chen,
Jeng-Liang Tsai,
Tanay Karnik:
HiSIM: hierarchical interconnect-centric circuit simulator.
ICCAD 2004: 489-496 |
| 8 |  | Jeng-Liang Tsai,
Tsung-Hao Chen,
Charlie Chung-Ping Chen:
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 565-572 (2004) |
| 2003 |
| 7 |  | Tsung-Hao Chen,
Clement Luk,
Charlie Chung-Ping Chen:
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation.
ICCAD 2003: 786-792 |
| 6 |  | Rong Jiang,
Tsung-Hao Chen,
Charlie Chung-Ping Chen:
PODEA: Power delivery efficient analysis with realizable model reduction.
ISCAS (4) 2003: 608-611 |
| 5 |  | Jeng-Liang Tsai,
Tsung-Hao Chen,
Charlie Chung-Ping Chen:
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.
ISPD 2003: 166-173 |
| 4 |  | Tsung-Hao Chen,
Clement Luk,
Charlie Chung-Ping Chen:
INDUCTWISE: inductance-wise interconnect simulator and extractor.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 884-894 (2003) |
| 2002 |
| 3 |  | Yahong Cao,
Yu-Min Lee,
Tsung-Hao Chen,
Charlie Chung-Ping Chen:
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery.
DAC 2002: 379-384 |
| 2 |  | Tsung-Hao Chen,
Clement Luk,
Hyungsuk Kim,
Charlie Chung-Ping Chen:
INDUCTWISE: inductance-wise interconnect simulator and extractor.
ICCAD 2002: 215-220 |
| 2001 |
| 1 |  | Tsung-Hao Chen,
Charlie Chung-Ping Chen:
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods.
DAC 2001: 559-562 |