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| 2010 | ||
|---|---|---|
| 66 | Allen Chen, Ryan Hoppal, Tom Chen: On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications. DSD 2010: 628-634 | |
| 65 | Zach Cashero, Allen Chen, Ryan Hoppal, Tom Chen: Fast Evaluation of Analog Circuits Using Linear Programming. ISVLSI 2010: 253-258 | |
| 64 | Charles Thangaraj, Robert Pownall, Phil Nikkel, Guangwei Yuan, Kevin L. Lear, Tom Chen: Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery. IEEE Trans. VLSI Syst. 18(10): 1385-1398 (2010) | |
| 63 | Charles Thangaraj, Alkan Cengiz, Tom Chen: Rapid design space exploration using legacy design data and technology scaling trend. Integration 43(2): 202-219 (2010) | |
| 2008 | ||
| 62 | Charles Thangaraj, Tom Chen: Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. DELTA 2008: 539-544 | |
| 61 | Charles Thangaraj, Tom Chen: Design target exploration for meeting time-to-market using pareto analysis. ISCAS 2008: 364-367 | |
| 2007 | ||
| 60 | Charles Thangaraj, Tom Chen: Power andPerformance Analysis for Early Design Space Exploration. ISVLSI 2007: 473-478 | |
| 59 | Daniela De Venuto, Tom Chen: Editorial. Microelectronics Journal 38(4-5): 453 (2007) | |
| 2006 | ||
| 58 | Jayashree Sridharan, Tom Chen: Modeling multiple input switching of CMOS gates in DSM technology using HDMR. DATE 2006: 626-631 | |
| 57 | Jayashree Sridharan, Tom Chen: Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. VLSI Design 2006: 323-328 | |
| 2005 | ||
| 56 | Vinil Varghese, Tom Chen, Peter Young: Stability analysis of active clock deskewing systems using a control theoretic approach. ASP-DAC 2005: 600-605 | |
| 55 | John Pratt, Mahir Aydin, Tom Chen: RC Extraction of Interconnects at Sub-Wavelength Dimensions. Artificial Intelligence and Applications 2005: 491-496 | |
| 54 | Vinil Varghese, Tom Chen, Peter Michael Young: Systematic Analysis of Active Clock Deskewing Systems Using Control Theory. DATE 2005: 820-825 | |
| 53 | Ajith Chandy, Tom Chen: Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. DATE 2005: 984-985 | |
| 52 | Medha Kulkarni, Tom Chen: A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1336-1346 (2005) | |
| 51 | Daniela De Venuto, Tom Chen: International Symposium on Quality Electronic Design. Microelectronics Journal 36(9): 787-788 (2005) | |
| 2004 | ||
| 50 | Gerald Esch Jr., Tom Chen: Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations. DELTA 2004: 312-320 | |
| 49 | Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen: RUBASTEM: A Method for Testing VHDL Behavioral Models. HASE 2004: 187-196 | |
| 48 | Medha Kulkarni, Tom Chen: A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. ISQED 2004: 331-336 | |
| 47 | Gerald Esch Jr., Tom Chen: Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. IEEE Trans. VLSI Syst. 12(11): 1253-1257 (2004) | |
| 46 | Tom Chen, Amjad Hajjar: Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1677-1683 (2004) | |
| 45 | Geun Rae Cho, Tom Chen: Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 229-242 (2004) | |
| 2003 | ||
| 44 | Tom Chen, Amjad Hajjar: Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. ISQED 2003: 183-188 | |
| 43 | Geun Rae Cho, Tom Chen: Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED 2003: 55-60 | |
| 42 | Geun Rae Cho, Tom Chen: On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. VLSI Design 2003: 513- | |
| 41 | Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen: A Rule-Based Software Testing Method for VHDL Models. VLSI-SOC 2003: 92- | |
| 40 | Jinsang Kim, Tom Chen: A VLSI architecture for video-object segmentation. IEEE Trans. Circuits Syst. Video Techn. 13(1): 83-96 (2003) | |
| 2002 | ||
| 39 | Amjad Hajjar, Tom Chen: An Accurate Coverage Forecasting Model for Behavioral Model Verification. DELTA 2002: 104-110 | |
| 38 | Geun Rae Cho, Tom Chen: On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ICCD 2002: 322-326 | |
| 37 | Amjad Hajjar, Tom Chen: Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. ISQED 2002: 304-309 | |
| 36 | Geun Rae Cho, Tom Chen: Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ISQED 2002: 458-463 | |
| 35 | Geun Rae Cho, Tom Chen: On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS 2002: 289-294 | |
| 34 | Tom Chen, Andre Bai, Amjad Hajjar, Anneliese Amschler Andrews, Charles Anderson: Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification. J. Electronic Testing 18(6): 583-594 (2002) | |
| 2001 | ||
| 33 | Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman: High quality behavioral verification using statistical stopping criteria. DATE 2001: 411-419 | |
| 32 | Tom Chen: On the impact of on-chip inductance on signal nets under the influence of power grid noise. DATE 2001: 451-459 | |
| 31 | Tom Chen: Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. ISQED 2001: 173-178 | |
| 30 | Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman: Stopping Criteria Comparison: Towards High Quality Behavioral Verification. ISQED 2001: 31-37 | |
| 29 | Jinsang Kim, Tom Chen: Real-time Video Objects Segmentation using a Highly Pipelined Microarchitecture. VIIP 2001: 483-488 | |
| 28 | Jinsang Kim, Tom Chen: Multiple feature clustering for image sequence segmentation. Pattern Recognition Letters 22(11): 1207-1217 (2001) | |
| 2000 | ||
| 27 | Jinsang Kim, Tom Chen: A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. CAMP 2000: 57- | |
| 26 | Jinsang Kim, Tom Chen: Segmentation of Image Sequences Using SOFM Networks. ICPR 2000: 3877-3880 | |
| 25 | Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu: Achieving the Quality of Verification for Behavioral Models with Minimum Effort. ISQED 2000: 234- | |
| 1999 | ||
| 24 | Von-Kyoung Kim, Tom Chen, Mick Tegethoff: Fault Coverage Estimation for Early Stage of VLSI Design. Great Lakes Symposium on VLSI 1999: 105-108 | |
| 23 | Von-Kyoung Kim, Tom Chen: Assessing Defect Coverage of Memory Testing Algorithms. Great Lakes Symposium on VLSI 1999: 340- | |
| 22 | Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu: How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing. HASE 1999: 249-256 | |
| 21 | Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar: Efficient Verification of Behavioral Models Using Sequential Sampling Technique. VLSI 1999: 398-406 | |
| 20 | Amjad Hajjar, Tom Chen: VLSI Architecture for Real-Time Edge Linking. IEEE Trans. Pattern Anal. Mach. Intell. 21(1): 89-94 (1999) | |
| 19 | Tom Chen, Glen Sunada, Jain Jin: COBRA: a 100-MOPS single-chip programmable and expandable FFT. IEEE Trans. VLSI Syst. 7(2): 174-182 (1999) | |
| 18 | Von-Kyoung Kim, Tom Chen: On comparing functional fault coverage and defect coverage for memory testing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1676-1683 (1999) | |
| 1998 | ||
| 17 | Anneliese von Mayrhauser, Andre Bai, Tom Chen, Charles Anderson, Amjad Hajjar: Fast Antirandom (FAR) Test Generation. HASE 1998: 262-269 | |
| 1997 | ||
| 16 | Chien-Chih Chen, Tom Chen: Modified Rate-Distortion Function with Optimal Classification for Wavelet Coding. ICIP (3) 1997: 86-89 | |
| 15 | Von-Kyoung Kim, Tom Chen, Mick Tegethoff: ASIC Manufacturing Test Cost Prediction at Early Design Stage. ITC 1997: 356-361 | |
| 14 | Mick Tegethoff, Tom Chen: Simulation Techniques for the Manufacturing Test of MCMs. J. Electronic Testing 10(1-2): 137-149 (1997) | |
| 13 | Fahad M. Alzahrani, Tom Chen: A Real-Time Edge Detector: Algorithm and VLSI Architecture. Real-Time Imaging 3(5): 363-378 (1997) | |
| 1996 | ||
| 12 | Charles Anderson, Anneliese von Mayrhauser, Tom Chen: Assessing Neural Networks as Guides for Testing Activities. IEEE METRICS 1996: 155-165 | |
| 11 | Von-Kyoung Kim, Mick Tegethoff, Tom Chen: ASIC Yield Estimation at Early Design Cycle. ITC 1996: 590-594 | |
| 10 | Mick Tegethoff, Tom Chen: Sensitivity Analysis of Critical Parameters in Board Test. IEEE Design & Test of Computers 13(1): 58-63 (1996) | |
| 1994 | ||
| 9 | Fahad M. Alzahrani, Tom Chen: On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. ICCD 1994: 132-137 | |
| 8 | Glen Sunada, Jain Jin, Matt Berzins, Tom Chen: COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. ICCD 1994: 546-550 | |
| 7 | Mick Tegethoff, Tom Chen: Defects, Fault Coverage, Yield and Cost in Board Manufacturing. ITC 1994: 539-547 | |
| 6 | Mick Tegethoff, Tom Chen: Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. ITC 1994: 903-910 | |
| 1993 | ||
| 5 | Tom Chen, Glen Sunada: Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. IEEE Trans. VLSI Syst. 1(2): 88-97 (1993) | |
| 4 | Tom Chen, Li Zhu: An expandable column fft architecture using circuit switching networks. VLSI Signal Processing 6(3): 243-257 (1993) | |
| 1992 | ||
| 3 | Tom Chen, Glen Sunada: An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. ICCD 1992: 576-581 | |
| 2 | Tom Chen, Glen Sunada: A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. ITC 1992: 623-631 | |
| 1991 | ||
| 1 | Tom Chen, Li Zhu: A Fast 1024-Point FFT Architecture. ICPP (1) 1991: 646-647 | |
Colors in the list of coauthors
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