 | 2010 |
|---|
| 6 |       | Yi-Ming Lin,
Wan-Ching Liu,
Li-Yuan Chang,
Chih-Yuan Lien,
Pei-Yin Chen,
Shung-Chih Chen:
A low-power IP design of Viterbi decoder with dynamic threshold setting.
ISCAS 2010: 585-588 |
| 1997 |
|---|
| 5 | | Shung-Chih Chen,
Jer-Min Jou:
Diagnostic fault simulation for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 299-308 (1997) |
| 4 | | Shung-Chih Chen,
Jer-Min Jou:
Serial diagnostic fault simulation for synchronous sequential circuits.
Integration 23(2): 157-170 (1997) |
| 1995 |
|---|
| 3 |  | Jer-Min Jou,
Shung-Chih Chen:
Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning.
ISCAS 1995: 2004-2007 |
| 1994 |
|---|
| 2 | | Jer-Min Jou,
Shung-Chih Chen:
A fast and memory-efficient diagnostic fault simulation for sequential circuits.
ICCAD 1994: 723-726 |
| 1 | | Jer-Min Jou,
Shung-Chih Chen,
Ren-Der Chen:
A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits.
ISCAS 1994: 85-88 |
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