 | 2007 |
|---|
| 9 |       | Oscal T.-C. Chen,
Li-Hsun Chen:
A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding.
EURASIP J. Adv. Sig. Proc. 2007: (2007) |
| 8 | | Oscal T.-C. Chen,
Li-Hsun Chen,
N.-W. Lin,
Chih-Chang Chen:
Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs.
IEEE Trans. Circuits Syst. Video Techn. 17(1): 26-42 (2007) |
| 2006 |
|---|
| 7 | | Li-Hsun Chen,
Oscal T.-C. Chen:
A Low-Power Folded Programmable FIR Architecture.
SiPS 2006: 188-193 |
| 2005 |
|---|
| 6 | | Li-Hsun Chen,
Oscal T.-C. Chen:
A hardware-efficient FIR architecture with input-data and tap folding.
ISCAS (1) 2005: 544-547 |
| 5 | | Li-Hsun Chen,
Oscal T.-C. Chen,
Teng-Yi Wang,
Yung-Cheng Ma:
A multiplication-accumulation computation unit with optimized compressors and minimized switching activities.
ISCAS (6) 2005: 6118-6121 |
| 2004 |
|---|
| 4 |  | Li-Hsun Chen,
Oscal T.-C. Chen,
Teng-Yi Wang,
Chi-Lung Wang:
An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder.
ISCAS (2) 2004: 157-160 |
| 2003 |
|---|
| 3 | | Li-Hsun Chen,
Oscal T.-C. Chen,
Ruey-Ling Ma:
A high-efficiency reconfigurable digital signal processor for multimedia computing.
ISCAS (2) 2003: 768-771 |
| 2002 |
|---|
| 2 | | Li-Hsun Chen,
Wei-Lung Liu,
Oscal T.-C. Chen,
Ruey-Liang Ma:
A reconfigurable digital signal processor architecture for high-efficiency MPEG-4 video encoding.
ICME (2) 2002: 165-168 |
| 2001 |
|---|
| 1 | | Li-Hsun Chen,
Oscal T.-C. Chen:
A low-complexity and high-speed Booth-algorithm FIR architecture.
ISCAS (4) 2001: 338-341 |
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