Jwu E. Chen

	2009
46		Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. VLSI Syst. 17(2): 306-311 (2009)
	2007
45		Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1625-1636 (2007)
44		Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electronic Testing 23(4): 341-355 (2007)
	2006
43		Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen: IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371
42		Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu: A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC 2006: 1-8
41		Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen: IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2513-2525 (2006)
	2005
40		Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Oscillation ring based interconnect test scheme for SOC. ASP-DAC 2005: 184-187
39		Shih Ping Lin, Chung-Len Lee, Jwu E. Chen: A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium 2005: 224-229
38		Shih Ping Lin, Chung-Len Lee, Jwu E. Chen: Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium 2005: 324-329
37		Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen: Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium 2005: 360-365
36		Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen: Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36
	2004
35		Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium 2004: 145-150
34		Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen: A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. Asian Test Symposium 2004: 58-61
	2003
33		Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. 19(4): 637-651 (2003)
	2002
32		Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen: A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. Asian Test Symposium 2002: 170-175
31		Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen: An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. DATE 2002: 1119
30		Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electronic Testing 18(6): 571-581 (2002)
	2001
29		Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen: Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. Asian Test Symposium 2001: 151-156
28		Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Fault Diagnosis for Linear Analog Circuits. J. Electronic Testing 17(6): 483-494 (2001)
	2000
27		Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Fault diagnosis for linear analog circuits. Asian Test Symposium 2000: 25-30
26		Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen: Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium 2000: 338-343
25		Chin-Te Kao, Sam Wu, Jwu E. Chen: A case study of failure analysis and guardband determination for a 64M-bit DRAM. Asian Test Symposium 2000: 447-
24		Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su: A methodology for fault model development for hierarchical linear systems. Asian Test Symposium 2000: 90-95
23		Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir: Oscillation Ring Delay Test for High Performance Microprocessors. J. Electronic Testing 16(1-2): 147-155 (2000)
22		Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su: A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16(5): 751-766 (2000)
	1999
21		Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen: A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. J. Inf. Sci. Eng. 15(6): 885-897 (1999)
	1998
20		Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen: Maximization of power dissipation under random excitation for burn-in testing. ITC 1998: 567-576
19		Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS 1998: 341-347
18		Wen Ching Wu, Chung-Len Lee, Jwu E. Chen: A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. 14(3): 669-686 (1998)
	1997
17		Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen: Fault diagnosis of odd-even sorting networks. Asian Test Symposium 1997: 288-
16		Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Functional test pattern generation for CMOS operational amplifier. VTS 1997: 267-273
15		Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Identifying invalid states for sequential circuit test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1025-1033 (1997)
	1996
14		Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium 1996: 10-15
13		Jwu E. Chen: Yield Improvement by Test Error Cancellation. Asian Test Symposium 1996: 258-262
	1995
12		Wen Ching Wu, Chung-Len Lee, Jwu E. Chen: Identification of robust untestable path delay faults. Asian Test Symposium 1995: 229-
11		Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen: Fanout fault analysis for digital logic circuits. Asian Test Symposium 1995: 33-39
10		Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Factorization of Multi-Valued Logic Functions. ISMVL 1995: 164-169
9		Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Identifying Untestable Faults in Sequential Circuits. IEEE Design & Test of Computers 12(3): 14-23 (1995)
	1994
8		Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee: TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. EDAC-ETC-EUROASIC 1994: 508-512
7		Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin: Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC 1994: 661
6		Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Complete Test Set for Multiple-Valued Logic Networks. ISMVL 1994: 289-296
5		Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. ISMVL 1994: 44-51
	1992
4		Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. ISMVL 1992: 181-188
	1991
3		Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen: Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1559-1568 (1991)
2		Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen: Checkpoints in irredundant two-level combinational circuits. J. Electronic Testing 2(4): 395-397 (1991)
	1990
1		Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen: Single-fault fault collapsing analysis in sequential logic circuits. ITC 1990: 809-814

Coauthor Index

1	Magdy S. Abadir	[23]
2	Chi Peng Chang	[32]
3	Soon-Jyh Chang	[16] [30] [33]
4	Yao-Wen Chang	[36] [41] [43] [45]
5	Yeong-Jar Chang	[22]
6	Beyin Chen	[11]
7	Guan-Xun Chen	[34]
8	Ji-Jan Chen	[42]
9	J.-W. Hsia	[29]
10	Chih Wei Hu	[17]
11	Kuo-Chan Huang	[20] [21]
12	Yin-Chao Huang	[24]
13	R.-L. Jiang	[29]
14	Tagin Jiang	[37]
15	Chin-Te Kao	[25]
16	Chung-Len Lee	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [26] [27] [28] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46]
17	Katherine Shu-Min Li	[35] [36] [37] [40] [41] [43] [44] [45] [46]
18	Hsing-Chung Liang	[9] [14] [15] [19]
19	Jun-Weir Lin	[24] [27] [28] [31]
20	Meng Chiy Lin	[8]
21	Shih Ping Lin	[38] [39] [42]
22	Won Yih Lin	[7]
23	Chih-Wen Lu	[26]
24	Kun-Lun Luo	[42]
25	Wen-Zen Shen	[1] [2] [3] [11]
26	Chauchin Su	[22] [24] [26] [27] [28] [35] [36] [37] [40] [41] [43] [44] [45] [46]
27	Chih-Hu Wang	[29]
28	Hui Min Wang	[4] [5] [6] [10]
29	Mill-Jer Wang	[29]
30	Ming Shae Wu	[23] [32]
31	Sam Wu	[25]
32	Wen Ching Wu	[7] [12] [17] [18] [23] [42]

Colors in the list of coauthors

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