Jih-Jeen Chen

	2003
5		Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee: Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 363-370 (2003)
	2002
4		Kuen-Jong Lee, Jih-Jeen Chen: Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. Asian Test Symposium 2002: 338-
	2000
3		Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen: Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium 2000: 453-458
	1999
2		Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Broadcasting test patterns to multiple circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1793-1802 (1999)
	1998
1		Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Using a single input to support multiple scan chains. ICCAD 1998: 74-78

Coauthor Index

1	Cheng-Hua Huang	[1] [2]
2	Tsung-Chu Huang	[3]
3	Kuen-Jong Lee	[1] [2] [3] [4] [5]
4	Chia-Kai Yang	[5]

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