 | 2010 |
| 16 |  | Lei Wang,
Leibo Liu,
Hongyi Chen:
An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL.
IEEE Trans. on Circuits and Systems 57-II(6): 421-425 (2010) |
| 15 |  | Tuo Wu,
Hongyi Chen,
Dahong Qian:
A Novel Adaptive Current Biased Linear Radio-Frequency Power amplifier on SiGe HBT Process.
Journal of Circuits, Systems, and Computers 19(5): 1077-1088 (2010) |
| 14 |  | Haixin Wang,
Guoqiang Bai,
Hongyi Chen:
A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform.
Signal Processing Systems 58(3): 311-324 (2010) |
| 2009 |
| 13 |  | Bo Qin,
Hongyi Chen,
Xin Wang,
Albert Z. Wang,
Yinghui Hao,
Lee Yang,
Bin Zhao:
A Single-chip 33pJ/pulse 5th-derivative Gaussian based IR-UWB Transmitter in 0.13µm CMOS.
ISCAS 2009: 401-404 |
| 12 |  | Lei Wang,
Leibo Liu,
Hongyi Chen:
A Fast-locking and Wide-range Reversible SAR DLL.
ISCAS 2009: 992-995 |
| 2008 |
| 11 |  | Haixin Wang,
Guoqiang Bai,
Hongyi Chen:
Zodiac: System architecture implementation for a high-performance Network Security Processor.
ASAP 2008: 91-96 |
| 10 |  | Gang Chen,
Guoqiang Bai,
Hongyi Chen:
A dual-field elliptic curve cryptographic processor based on a systolic arithmetic unit.
ISCAS 2008: 3298-3301 |
| 9 |  | Hongyi Chen,
Dundar F. Kocaoglu:
A sensitivity analysis algorithm for hierarchical decision models.
European Journal of Operational Research 185(1): 266-288 (2008) |
| 2007 |
| 8 |  | Li Zhang,
Baoyong Chi,
Zhihua Wang,
Hongyi Chen,
Jinke Yao,
Ende Wu:
A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop.
ISCAS 2007: 2447-2450 |
| 7 |  | Haolu Xie,
Xin Wang,
Albert Z. Wang,
Bo Qin,
Hongyi Chen,
Yumei Zhou,
Bin Zhao:
A Varying Pulse Width Second Order Derivative Gaussian Pulse Generator for UWB Transceivers in CMOS.
ISCAS 2007: 2794-2797 |
| 6 |  | Haixin Wang,
Yao Yue,
Chunming Zhang,
Guoqiang Bai,
Hongyi Chen:
A Novel Unified Control Architecture for a High-Performance Network Security Accelerator.
Security and Management 2007: 573-579 |
| 5 |  | Gang Chen,
Guoqiang Bai,
Hongyi Chen:
A New Systolic Architecture for Modular Division.
IEEE Trans. Computers 56(2): 282-286 (2007) |
| 2005 |
| 4 |  | Chunjiang Tu,
Boan Liu,
Hongyi Chen:
An Analog Correlator for Ultra-Wideband Receivers.
EURASIP J. Adv. Sig. Proc. 2005(3): 455-461 (2005) |
| 2003 |
| 3 |  | Xingjun Wu,
Hongyi Chen,
Yihe Sun,
Weixin Gai:
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.
VLSI Signal Processing 33(1-2): 191-197 (2003) |
| 2002 |
| 2 |  | Leibo Liu,
Xuejin Wang,
Hongying Meng,
Li Zhang,
Zhihua Wang,
Hongyi Chen:
A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT.
APCCAS (2) 2002: 299-304 |
| 2001 |
| 1 |  | Lei Xu,
Yihe Sun,
Hongyi Chen:
Scan array solution for testing power and testing time.
ITC 2001: 652-659 |