Dianyong Chen

	2009
6		Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski: A full-rate truly monolithic CMOS CDR for low-cost applications. CCECE 2009: 1208-1212
5		Dianyong Chen, Bo Wang, Bangli Liang, Tad A. Kwasniewski: A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously. CCECE 2009: 1213-1216
4		Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tad A. Kwasniewski: A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. CCECE 2009: 1221-1226
3		Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tadeusz Kwasniewski: Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel. UKSim 2009: 574-578
2		Dianyong Chen, Bo Wang, Bangli Liang, Tadeusz Kwasniewski: A Simulator for High-Speed Backplane Transceivers. UKSim 2009: 589-593
	2008
1		Bangli Liang, Tad A. Kwasniewski, Dianyong Chen: A 42-Gb/s Decision Circuit in 0.13µm CMOS. CNSR 2008: 339-342

Coauthor Index

1	Jinguang Jiang	[3] [4]
2	Tad A. Kwasniewski (Tadeusz Kwasniewski)	[1] [2] [3] [4] [5] [6]
3	Bangli Liang	[1] [2] [3] [4] [5] [6]
4	Guohui Situ	[6]
5	Bo Wang	[2] [3] [4] [5] [6]
6	Zhigong Wang	[6]

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