![]() | ![]() |
| 2012 | ||
|---|---|---|
| 64 | Yun Liang, Zheng Cui, Shengkui Zhao, Kyle Rupnow, Yihao Zhang, Douglas L. Jones, Deming Chen: Real-time implementation and performance optimization of 3D sound localization on GPUs. DATE 2012: 832-835 | |
| 63 | Lu Wan, Deming Chen: Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 662-675 (2012) | |
| 62 | Lu Wan, Chen Dong, Deming Chen: A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance. Int. J. Reconfig. Comp. 2012: (2012) | |
| 61 | Yun Liang, Kyle Rupnow, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen: High-Level Synthesis: Productivity, Performance, and Software Constraints. J. Electrical and Computer Engineering 2012: (2012) | |
| 2011 | ||
| 60 | Janet Meiling Wang, Deming Chen: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011 IEEE 2011 | |
| 59 | Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen: Routing with graphene nanoribbons. ASP-DAC 2011: 323-329 | |
| 58 | Chi-Chen Peng, Chen Dong, Deming Chen: SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power. ASP-DAC 2011: 388-393 | |
| 57 | Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong: Multilevel Granularity Parallelism Synthesis on FPGAs. FCCM 2011: 178-185 | |
| 56 | Kyle Rupnow, Yun Liang, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen: High level synthesis of stereo matching: Productivity, performance, and software constraints. FPT 2011: 1-8 | |
| 55 | Artem Rogachev, Lu Wan, Deming Chen: Temperature aware statistical static timing analysis. ICCAD 2011: 103-110 | |
| 54 | Chen Dong, Chen Chen, Subhasish Mitra, Deming Chen: Architecture and performance evaluation of 3D CMOS-NEM FPGA. SLIP 2011: 1-8 | |
| 2010 | ||
| 53 | Quang Dinh, Deming Chen, Martin D. F. Wong: Dynamic power estimation for deep submicron circuits with process variation. ASP-DAC 2010: 587-592 | |
| 52 | Ying-Yu Chen, Chen Dong, Deming Chen: Clock tree synthesis under aggressive buffer insertion. DAC 2010: 86-89 | |
| 51 | Gregory Lucas, Chen Dong, Deming Chen: Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. FPGA 2010: 177-180 | |
| 50 | Gregory Lucas, Deming Chen: Variation-aware layout-driven scheduling for performance yield optimization. ICCAD 2010: 17-24 | |
| 49 | Lu Wan, Deming Chen: Analysis of circuit dynamic behavior with timed ternary decision diagram. ICCAD 2010: 516-523 | |
| 48 | Quang Dinh, Deming Chen, Martin D. F. Wong: BDD-based circuit restructuring for reducing dynamic power. ICCD 2010: 548-554 | |
| 47 | Deming Chen, Jason Cong, Yiping Fan, Lu Wan: LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. IEEE Trans. VLSI Syst. 18(4): 564-577 (2010) | |
| 46 | Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng: Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1709-1722 (2010) | |
| 45 | Gregory Lucas, Chen Dong, Deming Chen: Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1818-1822 (2010) | |
| 44 | Quang Dinh, Deming Chen, Martin D. F. Wong: A Routing Approach to Reduce Glitches in Low Power FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 235-240 (2010) | |
| 43 | Shoaib Akram, Alexandros Papakonstantinou, Rakesh Kumar, Deming Chen: A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. Int. J. Reconfig. Comp. 2010: (2010) | |
| 2009 | ||
| 42 | Gregory Lucas, Scott Cromar, Deming Chen: FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization. ASP-DAC 2009: 61-66 | |
| 41 | Scott Cromar, Jaeho Lee, Deming Chen: FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. DAC 2009: 838-843 | |
| 40 | Chen Dong, Scott Chilstedt, Deming Chen: Reconfigurable circuit design with nanomaterials. DATE 2009: 442-447 | |
| 39 | Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122 | |
| 38 | Chen Dong, Scott Chilstedt, Deming Chen: FPCNA: a field programmable carbon nanotube array. FPGA 2009: 161-170 | |
| 37 | Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles: Blueshift: Designing processors for timing speculation from the ground up. HPCA 2009: 213-224 | |
| 36 | Lu Wan, Deming Chen: DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior. ICCAD 2009: 172-179 | |
| 35 | Chun He, Alexandros Papakonstantinou, Deming Chen: A novel SoC architecture on FPGA for ultra fast face detection. ICCD 2009: 412-418 | |
| 34 | Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu: High-performance CUDA kernel execution on FPGAs. ICS 2009: 515-516 | |
| 33 | Quang Dinh, Deming Chen, Martin D. F. Wong: A routing approach to reduce glitches in low power FPGAs. ISPD 2009: 99-106 | |
| 32 | Chen Dong, Scott Chilstedt, Deming Chen: Variation Aware Routing for Three-Dimensional FPGAs. ISVLSI 2009: 298-303 | |
| 31 | Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu: FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. SASP 2009: 35-42 | |
| 30 | Shoaib Akram, Rakesh Kumar, Deming Chen: Workload adaptive shared memory multicore processors with reconfigurable interconnects. SASP 2009: 7-14 | |
| 29 | Deming Chen: Design Automation for Microelectronics. Handbook of Automation 2009: 653-670 | |
| 28 | Scott Chilstedt, Chen Dong, Deming Chen: Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture. International Journal of Parallel Programming 37(4): 389-416 (2009) | |
| 27 | Deming Chen, Scott Cromar: An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power. J. Low Power Electronics 5(4): 454-463 (2009) | |
| 2008 | ||
| 26 | Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen: VEBoC: Variation and error-aware design for billions of devices on a chip. ASP-DAC 2008: 803-808 | |
| 25 | Quang Dinh, Deming Chen, Martin D. F. Wong: Efficient ASIP design for configurable processors with fine-grained resource sharing. FPGA 2008: 99-106 | |
| 24 | Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu: Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor. SASP 2008: 20-25 | |
| 23 | Lei Cheng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) | |
| 22 | Lei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1203-1213 (2008) | |
| 2007 | ||
| 21 | Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang: High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534 | |
| 20 | Lei Cheng, Deming Chen, Martin D. F. Wong: GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. DAC 2007: 318-323 | |
| 19 | Lei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. DAC 2007: 910-915 | |
| 18 | Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig: Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375 | |
| 17 | Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang: Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. ICCAD 2007: 758-764 | |
| 2006 | ||
| 16 | Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. DAC 2006: 117-120 | |
| 15 | Joey Y. Lin, Deming Chen, Jason Cong: Optimal simultaneous mapping and clustering for FPGA delay optimization. DAC 2006: 472-477 | |
| 14 | Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu: Optimality study of resource binding with multi-Vdds. DAC 2006: 580-585 | |
| 13 | Deming Chen, Jason Cong, Junjuan Xu: Optimal simultaneous module and multivoltage assignment for low power. ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006) | |
| 12 | Deming Chen, Jason Cong, Peichen Pan: FPGA Design Automation: A Survey. Foundations and Trends in Electronic Design Automation 1(3): (2006) | |
| 2005 | ||
| 11 | Deming Chen, Jason Cong, Junjuan Xu: Optimal module and voltage assignment for low-power. ASP-DAC 2005: 850-855 | |
| 10 | Ren Wang, Deming Chen, Qingquan Qian: Research of double loop optical fiber self-cicatrized network based on Neuron3150. ISADS 2005: 352-355 | |
| 9 | Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong: Power modeling and characteristics of field programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1712-1724 (2005) | |
| 2004 | ||
| 8 | Deming Chen, Jason Cong: Register binding and port assignment for multiplexer optimization. ASP-DAC 2004: 68-73 | |
| 7 | Deming Chen, Jason Cong, Fei Li, Lei He: Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117 | |
| 6 | Deming Chen, Jason Cong: DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. ICCAD 2004: 752-759 | |
| 5 | Deming Chen, Jason Cong: Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED 2004: 70-73 | |
| 2003 | ||
| 4 | Fei Li, Deming Chen, Lei He, Jason Cong: Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184 | |
| 3 | Deming Chen, Jason Cong, Yiping Fan: Low-power high-level synthesis for FPGA architectures. ISLPED 2003: 134-139 | |
| 2 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003) | |
| 2001 | ||
| 1 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47 | |
Colors in the list of coauthors
Last update Tue May 29 01:28:40 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page