![]() | ![]() |
| 2011 | ||
|---|---|---|
| 45 | Yi-Li Lin, Wei-Tso Chen, Alvin W. Y. Su, Da-Wei Chang, Chung-Ho Chen: A low cost, low power, high scalability and dependability processor-cluster platform. SIES 2011: 95-98 | |
| 44 | Chung-Ho Chen, Chih-Lun Lu: Optimum profit model based on order quantity, product price, and process quality level. Expert Syst. Appl. 38(6): 7886-7893 (2011) | |
| 43 | Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. IEEE Trans. VLSI Syst. 19(3): 516-520 (2011) | |
| 42 | Yi-Ying Tsai, Chung-Ho Chen: Energy-Efficient Trace Reuse Cache for Embedded Processors. IEEE Trans. VLSI Syst. 19(9): 1681-1694 (2011) | |
| 41 | Chung-Ho Chen, Chih-Lun Lu: Optimum profit model considering production, quality and sale problem. Int. J. Systems Science 42(12): 1917-1933 (2011) | |
| 2010 | ||
| 40 | Shye-Tzeng Shen, Shin-Ying Lee, Chung-Ho Chen: Full system simulation with QEMU: An approach to multi-view 3D GPU design. ISCAS 2010: 3877-3880 | |
| 39 | Chung-Ho Chen, Wan-Lin Chang: Optimal design of expected lifetime and warranty period for product with quality loss and inspection error. Expert Syst. Appl. 37(4): 3521-3526 (2010) | |
| 2009 | ||
| 38 | Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao: Full System Simulation and Verification Framework. IAS 2009: 165-168 | |
| 37 | Chung-Ho Chen, Michael B. C. Khoo: Optimum process mean and manufacturing quantity settings for serial production system under the quality loss and rectifying inspection plan. Computers & Industrial Engineering 57(3): 1080-1088 (2009) | |
| 36 | Chung-Ho Chen, Hui-Sung Kao: The determination of optimum process mean and screening limits based on quality loss function. Expert Syst. Appl. 36(3): 7332-7335 (2009) | |
| 2008 | ||
| 35 | Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen: Address compression for scalable load/store queue implementation. ISCAS 2008: 1680-1683 | |
| 34 | Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: A hybrid self-testing methodology of processor cores. ISCAS 2008: 3378-3381 | |
| 33 | Wei-Cheng Lin, Chung-Ho Chen: Avoiding unnecessary frame memory access and multi-frame motion estimation computation in H.264/AVC. ISCAS 2008: 632-635 | |
| 32 | Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen: Power-efficient and scalable load/store queue design via address compression. SAC 2008: 1523-1527 | |
| 31 | Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: A hybrid software-based self-testing methodology for embedded processor. SAC 2008: 1528-1534 | |
| 30 | Chung-Ho Chen: Economic Production Run Length and warranty Period for Product with Weibull Lifetime. APJOR 25(6): 753-764 (2008) | |
| 29 | Wei-Cheng Lin, Chung-Ho Chen: Frame Buffer Access Reduction for MPEG Video Decoder. IEEE Trans. Circuits Syst. Video Techn. 18(10): 1452-1456 (2008) | |
| 28 | Chung-Ming Chen, Chung-Ho Chen: Configurable VLSI Architecture for Deblocking Filter in H.264/AVC. IEEE Trans. VLSI Syst. 16(8): 1072-1082 (2008) | |
| 2007 | ||
| 27 | Wei-Cheng Lin, Chung-Ho Chen: Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG Video Encoder. ICCCN 2007: 817-820 | |
| 26 | Wei-Cheng Lin, Chung-Ho Chen: A data-reuse scheme for avoiding unnecessary memory accesses in MPEG-4 ASP video decoder. SoCC 2007: 243-246 | |
| 25 | Chung-Ho Chen, Min-Tsai Lai: Determining the optimum process mean based on quadratic quality loss function and rectifying inspection plan. European Journal of Operational Research 182(2): 755-763 (2007) | |
| 24 | Chung-Ho Chen, Min-Tsai Lai: Economic manufacturing quantity, optimum process mean, and economic specification limits setting under the rectifying inspection plan. European Journal of Operational Research 183(1): 336-344 (2007) | |
| 23 | Chung-Ho Chen, Kuo-Su Hsiao: Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality. IEEE Trans. Computers 56(11): 1534-1548 (2007) | |
| 22 | Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao: Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. IEEE Trans. VLSI Syst. 15(5): 505-517 (2007) | |
| 21 | Chung-Ming Chen, Chung-Ho Chen: An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC. IEICE Transactions 90-D(1): 99-107 (2007) | |
| 2006 | ||
| 20 | Kuo-Su Hsiao, Chung-Ho Chen: Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling. ICCD 2006 | |
| 19 | Wei-Cheng Lin, Chung-Ho Chen: Exploring reusable frame buffer data for MPEG-4 video decoding. ISCAS 2006 | |
| 18 | Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, Han-Chiang Chen: Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator. LCN 2006: 257-263 | |
| 17 | Chao-Yu Chou, Chun-Hua Chen, Chung-Ho Chen: Economic design of variable sampling intervals T2 control charts using genetic algorithms. Expert Syst. Appl. 30(2): 233-242 (2006) | |
| 2005 | ||
| 16 | Chung-Ming Chen, Chung-Ho Chen: An efficient VLSI architecture for edge filtering in H.264/AVC. Circuits, Signals, and Systems 2005: 118-122 | |
| 15 | Chung-Ming Chen, Chung-Ho Chen: An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding. Computer Graphics and Imaging 2005: 177-181 | |
| 14 | Kuo-Su Hsiao, Chung-Ho Chen: An efficient wakeup design for energy reduction in high-performance superscalar processors. Conf. Computing Frontiers 2005: 353-360 | |
| 2001 | ||
| 13 | Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen: Parameterized MAC unit implementation. ASP-DAC 2001: 23-24 | |
| 12 | Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo: A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001) | |
| 1999 | ||
| 11 | Chung-Ho Chen, Arun K. Somani: Fault Containment in Cache Memories for TMR Redundant Processor Systems. IEEE Trans. Computers 48(4): 386-397 (1999) | |
| 10 | Chung-Ho Chen, Feng-Fu Lin: An Easy-to-Use Approach for Practical Bus-Based System Design. IEEE Trans. Computers 48(8): 780-793 (1999) | |
| 1997 | ||
| 9 | Chung-Ho Chen, Akida Wu: Microarchitecture Support for Improving the Performance of Load Target Prediction. MICRO 1997: 228-234 | |
| 1996 | ||
| 8 | Chung-Ho Chen, Arun K. Somani: Architecture Technique Trade-Offs Using Mean Memory Delay Time. IEEE Trans. Computers 45(10): 1089-1100 (1996) | |
| 7 | Craig M. Wittenbrink, Arun K. Somani, Chung-Ho Chen: Cache write generate for parallel image processing on shared memory architectures. IEEE Transactions on Image Processing 5(7): 1204-1208 (1996) | |
| 1995 | ||
| 6 | Robert M. Haralick, Arun K. Somani, Craig M. Wittenbrink, Robert Johnson, Kenneth Cooper, Linda G. Shapiro, Ihsin T. Phillips, Jenq-Neng Hwang, William Cheung, Yung Hsi Yao, Chung-Ho Chen, Larry Yang, Brian Daugherty, Bob Lorbeski, Kent Loving, Tom Miller, Larye Parkins, Steve Soos: Proteus: A reconfigurable computational network for computer vision. Mach. Vis. Appl. 8(2): 85-100 (1995) | |
| 1994 | ||
| 5 | Chung-Ho Chen, Arun K. Somani: A Cache Protocol for Error Detection and Recovery in Fault-Tolerant Computing Systems. FTCS 1994: 278-287 | |
| 4 | Chung-Ho Chen, Arun K. Somani: A Unified Architectural Tradeoff Methodology. ISCA 1994: 348-357 | |
| 1992 | ||
| 3 | Chung-Ho Chen, Arun K. Somani: Effects of Cache Traffic on Shared Bus Multiprocessor Systems. ICPP (1) 1992: 285-288 | |
| 1991 | ||
| 2 | Arun K. Somani, Craig M. Wittenbrink, Robert M. Haralick, Linda G. Shapiro, Jenq-Neng Hwang, Chung-Ho Chen, Robert Johnson, Kenneth Cooper: Proteus System Architecture and Organization. IPPS 1991: 287-294 | |
| 1982 | ||
| 1 | Chung-Ho Chen: An Algebraic Model of Arithmetic Codes. IEEE Trans. Computers 31(4): 318-321 (1982) | |
Colors in the list of coauthors
Last update Tue May 29 01:28:40 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page