Chun-hong Chen

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1999

2 Chun-hong Chen, Chi-Ying Tsui: Timing Optimization of Logic Network Using Gate Duplication. ASP-DAC 1999: 233-236

1998

1 Chun-hong Chen, Chi-Ying Tsui: Towards the capability of providing power-area-delay trade-off at the register transfer level. ISLPED 1998: 24-29

	1999
2		Chun-hong Chen, Chi-Ying Tsui: Timing Optimization of Logic Network Using Gate Duplication. ASP-DAC 1999: 233-236
	1998
1		Chun-hong Chen, Chi-Ying Tsui: Towards the capability of providing power-area-delay trade-off at the register transfer level. ISLPED 1998: 24-29

Coauthor Index

1 Chi-Ying Tsui [1] [2]

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