Chien-In Henry Chen

	2011
30		Kumar Yelamarthi, Chien-In Henry Chen: Delay optimization considering power saving in dynamic CMOS circuits. ISQED 2011: 364-369
29		Kiran George, Chien-In Henry Chen: A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement. IEEE T. Instrumentation and Measurement 60(12): 3956-3958 (2011)
	2010
28		Kumar Yelamarthi, Chien-In Henry Chen: Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations. VLSI Design 2010: (2010)
	2009
27		Yu-Heng George Lee, Chien-In Henry Chen: Dual Thresholding for Digital Wideband Receivers with Variable Truncation Scheme. ISCAS 2009: 920-923
26		Kiran George, Chien-In Henry Chen: Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip. IEEE T. Instrumentation and Measurement 58(5): 1495-1504 (2009)
25		Yu-Heng George Lee, Chien-In Henry Chen: Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection. IEEE T. Instrumentation and Measurement 58(5): 1555-1562 (2009)
	2008
24		Yu-Heng George Lee, James Helton, Chien-In Henry Chen: Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver. ISCAS 2008: 2494-2497
23		Kumar Yelamarthi, Chien-In Henry Chen: Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ISQED 2008: 143-147
22		James Helton, Chien-In Henry Chen, David M. Lin, James B. Y. Tsui: FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver. ISQED 2008: 568-571
21		Xinhui Zhang, Chien-In Henry Chen, Arvindkumar Chakravarthy: Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test. IEEE T. Instrumentation and Measurement 57(3): 651-663 (2008)
20		Kumar Yelamarthi, Chien-In Henry Chen: Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. JCP 3(2): 21-28 (2008)
	2007
19		Kumar Yelamarthi, Chien-In Henry Chen: Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. ISQED 2007: 426-431
18		Mingzhen Wang, Chien-In Henry Chen: Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications. SoCC 2007: 109-112
17		Mingzhen Wang, Chien-In Henry Chen, Shailesh Radhakrishnan: Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS. IEEE T. Instrumentation and Measurement 56(3): 1064-1073 (2007)
16		Jason Wibbenmeyer, Chien-In Henry Chen: Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters. IEEE T. Instrumentation and Measurement 56(6): 2748-2756 (2007)
	2005
15		Shailesh Radhakrishnan, Mingzhen Wang, Chien-In Henry Chen: A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder. ISCAS (6) 2005: 6142-6145
14		Chien-In Henry Chen, Kiran George, William McCormick, James B. Y. Tsui, Stephen L. Hary, Keith M. Graves: Design and performance evaluation of a 2.5-GSPS digital receiver. IEEE T. Instrumentation and Measurement 54(3): 1089-1099 (2005)
	2004
13		Chien-In Henry Chen, Kiran George: Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test. IEEE T. Instrumentation and Measurement 53(4): 1005-1014 (2004)
	2003
12		Chien-In Henry Chen, Kiran George: Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. ISCAS (5) 2003: 521-524
11		Chien-In Henry Chen, Kiran George: Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. ISQED 2003: 111-
	2001
10		Chien-In Henry Chen: Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults. ISSS 2001: 203-208
	1999
9		Meghanad D. Wagh, Chien-In Henry Chen: High-level design synthesis with redundancy removal for high speed testable adders. ISCAS (6) 1999: 358-361
	1994
8		Chien-In Henry Chen, Anup Kumar: Comments on "Area-Time Optimal Adder Design". IEEE Trans. Computers 43(4): 507-512 (1994)
7		Chien-In Henry Chen, Joel T. Yuen: Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design. IEEE Trans. VLSI Syst. 2(3): 273-291 (1994)
	1993
6		Chien-In Henry Chen, Joel T. Yuen: Logic partitioning to pseudo-exhaustive test for BIST design. ICCAD 1993: 646-649
	1992
5		Chien-In Henry Chen, Joel T. Yuen: Concurrent Test Scheduling in Built-In Self-Test Environment. ICCD 1992: 256-259
4		Chien-In Henry Chen, Joel T. Yuen, Ji-Der Lee: Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment. ICCD 1992: 264-267
	1991
3		Chien-In Henry Chen: Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit. DAC 1991: 287-290
2		Chien-In Henry Chen: BISTSYN - A Built-In Self-Test Synthesizer. ICCAD 1991: 240-243
1		Chien-In Henry Chen: Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis. ICCD 1991: 418-421

Coauthor Index

1	Arvindkumar Chakravarthy	[21]
2	Kiran George	[11] [12] [13] [14] [26] [29]
3	Keith M. Graves	[14]
4	Stephen L. Hary	[14]
5	James Helton	[22] [24]
6	Anup Kumar	[8]
7	Ji-Der Lee	[4]
8	Yu-Heng George Lee	[24] [25] [27]
9	David M. Lin	[22]
10	William McCormick	[14]
11	Shailesh Radhakrishnan	[15] [17]
12	James B. Y. Tsui	[14] [22]
13	Meghanad D. Wagh	[9]
14	Mingzhen Wang	[15] [17] [18]
15	Jason Wibbenmeyer	[16]
16	Kumar Yelamarthi	[19] [20] [23] [28] [30]
17	Joel T. Yuen	[4] [5] [6] [7]
18	Xinhui Zhang	[21]

Colors in the list of coauthors

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