Che-Fu Chen

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1995

1 Chin-Liang Wang, Ching-Chia Chen, Che-Fu Chen: A Digital-Serial VLSI Architecture for Delayed LMS Adaptive FIR Filttering. ISCAS 1995: 545-548

	1995
1		Chin-Liang Wang, Ching-Chia Chen, Che-Fu Chen: A Digital-Serial VLSI Architecture for Delayed LMS Adaptive FIR Filttering. ISCAS 1995: 545-548

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