Pramit Chavda

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1998

1 Pramit Chavda, James Jacob, Vishwani D. Agrawal: Optimizing Logic Design Using Boolean Transforms. VLSI Design 1998: 218-221

	1998
1		Pramit Chavda, James Jacob, Vishwani D. Agrawal: Optimizing Logic Design Using Boolean Transforms. VLSI Design 1998: 218-221

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