Saurabh Chaudhury

	2011
5		Saurabh Chaudhury, Anirban Dutta: Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs. Circuits and Systems 2(3): 217-224 (2011)
	2010
4		Saurabh Chaudhury, Anirban Dutta: Genetic algorithm based variable ordering of BDDs for multi-level logic optimization with area-power trade-offs. ICECS 2010: 627-630
	2009
3		Saurabh Chaudhury, Krishna Teja Sistla, Santanu Chattopadhyay: Genetic algorithm-based FSM synthesis with area-power trade-offs. Integration 42(3): 376-384 (2009)
2		Saurabh Chaudhury, J. Srinivasa Rao, Santanu Chattopadhyay: State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis. J. Low Power Electronics 5(4): 464-473 (2009)
	2006
1		Saurabh Chaudhury, Santanu Chattopadhyay, J. Srinivasa Rao: Synthesis of Finite State Machines for Low Power and Testability. APCCAS 2006: 1434-1437

Coauthor Index

1	Santanu Chattopadhyay	[1] [2] [3]
2	Anirban Dutta	[4] [5]
3	J. Srinivasa Rao	[1] [2]
4	Krishna Teja Sistla	[3]

Colors in the list of coauthors

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