 | 2011 |
| 22 |  | Jayesh Gaur,
Mainak Chaudhuri,
Sreenivas Subramoney:
Bypass and insertion algorithms for exclusive last-level caches.
ISCA 2011: 81-92 |
| 2010 |
| 21 |  | Santhosh Sharma Ananthramu,
Deepak Majeti,
Sanjeev Kumar Aggarwal,
Mainak Chaudhuri:
Improving speculative loop parallelization via selective squash and speculation reuse.
PACT 2010: 543-544 |
| 2009 |
| 20 |  | Mainak Chaudhuri:
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.
HPCA 2009: 227-238 |
| 19 |  | Mainak Chaudhuri:
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.
MICRO 2009: 401-412 |
| 18 |  | B. C. Vishwas,
Abhishek Gadia,
Mainak Chaudhuri:
Implementing a parallel matrix factorization library on the cell broadband engine.
Scientific Programming 17(1-2): 3-29 (2009) |
| 2007 |
| 17 |  | Jugash Chandarlapati,
Mainak Chaudhuri:
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation.
ICCD 2007: 423-430 |
| 16 |  | Lakshmana Rao Vittanala,
Mainak Chaudhuri:
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors.
ICPP 2007: 4 |
| 15 |  | Dhiraj D. Kalamkar,
Mainak Chaudhuri,
Mark Heinrich:
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads.
ISPASS 2007: 242-253 |
| 14 |  | Arkaprava Basu,
Nevin Kirman,
Meyrem Kirman,
Mainak Chaudhuri,
José F. Martínez:
Scavenger: A New Last Level Cache Architecture with Global Block Priority.
MICRO 2007: 421-432 |
| 13 |  | Mainak Chaudhuri,
Mark Heinrich:
Integrated Memory Controllers with Parallel Coherence Streams.
IEEE Trans. Parallel Distrib. Syst. 18(8): 1159-1173 (2007) |
| 2006 |
| 12 |  | Abhas Kumar,
Nisheet Jain,
Mainak Chaudhuri:
Long-latency branches: how much do they matter?
SIGARCH Computer Architecture News 34(3): 9-15 (2006) |
| 2005 |
| 11 |  | Nevin Kirman,
Meyrem Kirman,
Mainak Chaudhuri,
José F. Martínez:
Checkpointed Early Load Retirement.
HPCA 2005: 16-27 |
| 2004 |
| 10 |  | Mainak Chaudhuri,
Mark Heinrich:
SMTp: An Architecture for Next-generation Scalable Multi-threading.
ISCA 2004: 124-137 |
| 9 |  | Daehyun Kim,
Mainak Chaudhuri,
Mark Heinrich,
Evan Speight:
Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems.
IEEE Trans. Computers 53(3): 288-307 (2004) |
| 8 |  | Mainak Chaudhuri,
Mark Heinrich:
The Impact of Negative Acknowledgments in Shared Memory Scientific Applications.
IEEE Trans. Parallel Distrib. Syst. 15(2): 134-150 (2004) |
| 7 |  | Mainak Chaudhuri,
Mark Heinrich:
Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols.
IEEE Trans. Parallel Distrib. Syst. 15(8): 699-712 (2004) |
| 2003 |
| 6 |  | Daehyun Kim,
Mainak Chaudhuri,
Mark Heinrich:
Active Memory Techniques for ccNUMA Multiprocessors.
IPDPS 2003: 10 |
| 5 |  | Mainak Chaudhuri,
Mark Heinrich,
Chris Holt,
Jaswinder Pal Singh,
Edward Rothberg,
John L. Hennessy:
Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation.
IEEE Trans. Computers 52(7): 862-880 (2003) |
| 4 |  | Mark Heinrich,
Mainak Chaudhuri:
Ocean warning: avoid drowning.
SIGARCH Computer Architecture News 31(3): 30-32 (2003) |
| 2002 |
| 3 |  | Daehyun Kim,
Mainak Chaudhuri,
Mark Heinrich:
Leveraging cache coherence in active memory systems.
ICS 2002: 2-13 |
| 2 |  | Mark Heinrich,
Evan Speight,
Mainak Chaudhuri:
Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters.
ISHPC 2002: 78-92 |
| 1 |  | Mainak Chaudhuri,
Daehyun Kim,
Mark Heinrich:
Cache Coherence Protocol Design for Active Memory Systems.
PDPTA 2002: 83-89 |