Santanu Chattopadhyay

	2012
55		Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur: A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection. VLSI Design 2012: 436-441
54		S. Krishna Kumar, Subhadip Kundu, Santanu Chattopadhyay: Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing. Integration 45(2): 211-221 (2012)
	2011
53		Pradip Kumar Sahu, Putta Venkatesh, Sunilraju Gollapalli, Santanu Chattopadhyay: Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization. ISVLSI 2011: 335-336
52		Soumya J., Putta Venkatesh, Santanu Chattopadhyay: Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis. ISVLSI 2011: 341-342
51		Santanu Kundu, Santanu Chattopadhyay: Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits. ISVLSI 2011: 357-358
50		Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur: Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. VLSI Design 2011: 364-369
49		Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay: Low power finite state machine synthesis using power-gating. Integration 44(3): 175-184 (2011)
48		Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay: And-or-XOR Network Synthesis with Area-Power Trade-Off. Journal of Circuits, Systems, and Computers 20(6): 1019-1035 (2011)
	2010
47		S. Krishna Kumar, S. Kaundinya, Santanu Chattopadhyay: Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing. Asian Test Symposium 2010: 401-406
46		S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay: Customizing pattern set for test power reduction via improved X-identification and reordering. ISLPED 2010: 177-182
	2009
45		Subhadip Kundu, Santanu Chattopadhyay: Efficient Don't Care Filling for Power Reduction during Testing. ARTCom 2009: 319-323
44		S. Krishna Kumar, P. Uday Bhaskar, Santanu Chattopadhyay, Pradip Mandal: Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing. ARTCom 2009: 346-350
43		Santanu Kundu, Kanchan Manna, Shobhit Gupta, Kundan Kumar, Ritesh Parikh, Santanu Chattopadhyay: A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic. ARTCom 2009: 414-418
42		Subhadip Kundu, S. Krishna Kumar, Santanu Chattopadhyay: Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption. Asian Test Symposium 2009: 307-312
41		Ajit Pal, Santanu Chattopadhyay: Synthesis & Testing for Low Power. VLSI Design 2009: 37-38
40		Saurabh Chaudhury, Krishna Teja Sistla, Santanu Chattopadhyay: Genetic algorithm-based FSM synthesis with area-power trade-offs. Integration 42(3): 376-384 (2009)
39		Saurabh Chaudhury, J. Srinivasa Rao, Santanu Chattopadhyay: State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis. J. Low Power Electronics 5(4): 464-473 (2009)
	2008
38		Santanu Kundu, Santanu Chattopadhyay: Mesh-of-tree deterministic routing for network-on-chip architecture. ACM Great Lakes Symposium on VLSI 2008: 343-346
37		Mayur Bubna, Naresh Shenoy, Santanu Chattopadhyay: An efficient greedy approach to PLA folding. ISCAS 2008: 1356-1359
36		Rafiahamed Shaik, Mrityunjoy Chakraborty, Santanu Chattopadhyay: An efficient finite precision realization of the block adaptive decision feedback equalizer. ISCAS 2008: 1910-1913
35		Tapas K. Maiti, Santanu Chattopadhyay: Don't care filling for power minimization in VLSI circuit testing. ISCAS 2008: 2637-2640
34		Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay: Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. ISVLSI 2008: 269-274
33		Santanu Kundu, Santanu Chattopadhyay: Network-on-chip architecture design based on mesh-of-tree deterministic routing topology. IJHPSA 1(3): 163-182 (2008)
	2007
32		Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay: Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling. ICCTA 2007: 141-145
31		Chandan Giri, B. Mallikarjuna Rao, Santanu Chattopadhyay: Test Data Compression by Spilt-VIHC (SVIHC). ICCTA 2007: 146-150
30		Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay: Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach. ICIC (2) 2007: 1032-1041
29		Chandan Giri, Santanu Chattopadhyay: Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs. ISCAS 2007: 3679-3682
28		Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay: A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. VLSI-SoC 2007: 320-323
	2006
27		Saurabh Chaudhury, Santanu Chattopadhyay, J. Srinivasa Rao: Synthesis of Finite State Machines for Low Power and Testability. APCCAS 2006: 1434-1437
	2005
26		Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay: Flip-flop chaining architecture for power-efficient scan during test application. Asian Test Symposium 2005: 410-413
25		Santanu Chattopadhyay, Manas Kumar Dewangan: A Combinational Logic Mapper for Actel's SX/AX Family. VLSI Design 2005: 669-672
24		Santanu Chattopadhyay: Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis?A Genetic Algorithm Approach. Comput. J. 48(4): 443-450 (2005)
	2004
23		Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay: Model checking on state transition diagram. ASP-DAC 2004: 412-417
22		D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar: Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs. VLSI Design 2004: 79-84
	2003
21		Santanu Chattopadhyay, K. Sudarsana Reddy: Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips. VLSI Design 2003: 341-346
20		Santanu Chattopadhyay, Naveen Choudhary: Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. VLSI Design 2003: 552-
19		Rohit Pandey, Santanu Chattopadhyay: Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach". VLSI Design 2003: 79-84
	2002
18		Santanu Chattopadhyay: Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata. Asian Test Symposium 2002: 188-193
	2001
17		Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay: A Novel Strategy to Test Core Based Designs. VLSI Design 2001: 122-127
16		Prabir Dasgupta, Santanu Chattopadhyay, Parimal Pal Chaudhuri, Indranil Sengupta: Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator. IEEE Trans. Computers 50(2): 177-185 (2001)
15		Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta: Theory and application of non-group cellular automata for message authentication. Journal of Systems Architecture 47(5): 383-404 (2001)
	2000
14		Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta: An ASIC for Cellular Automata Based Message Authentication. VLSI Design 2000: 538-
13		Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta: Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits. VLSI Design 2000: 544-549
	1998
12		Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri: Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. Asian Test Symposium 1998: 388-
11		Santanu Chattopadhyay, Parimal Pal Chaudhuri: Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis. VLSI Design 1998: 522-527
10		Santanu Chattopadhyay, Parimal Pal Chaudhuri: Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence. VLSI Design 1998: 564-
9		Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri: Cellular-Automata-Array-Based Diagnosis of Board Level Faults. IEEE Trans. Computers 47(8): 817-828 (1998)
	1997
8		Santanu Chattopadhyay, Parimal Pal Chaudhuri: Parallel Decoder for Cellular Automata Based Byte Error Correcting Code. VLSI Design 1997: 527-528
7		Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 257-265 (1997)
	1996
6		Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri: Cellular automata based architecture of a database query processor. VLSI Design 1996: 320-321
5		S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri: Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. VLSI Design 1996: 61-64
4		Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach. IEEE Trans. Computers 45(4): 487-490 (1996)
3		Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri: CAA Decoder for Cellular Automata Based Byte Error Correcting Code. IEEE Trans. Computers 45(9): 1003-1016 (1996)
	1995
2		Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri: Board level fault diagnosis using cellular automata array. VLSI Design 1995: 343-348
1		Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. VLSI Design 1995: 57-62

Coauthor Index

1	Debabrata Bagchi	[17]
2	P. Uday Bhaskar	[44]
3	Subarna Bhattacharjee	[2] [9]
4	Mayur Bubna	[37]
5	Mrityunjoy Chakraborty	[36]
6	Parimal Pal Chaudhuri	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [16]
7	Saurabh Chaudhury	[27] [39] [40]
8	Naveen Choudhary	[20]
9	Dipanwita Roy Chowdhury	[2] [9] [17]
10	Batsayan Das	[23]
11	Prabir Dasgupta	[13] [14] [15] [16]
12	Manas Kumar Dewangan	[25]
13	Chandan Giri	[28] [29] [30] [31] [32]
14	Sunilraju Gollapalli	[53]
15	Shantanu Gupta	[26]
16	Shobhit Gupta	[43]
17	Soumya J.	[52]
18	Rohit Kapur	[50] [55]
19	S. Kaundinya	[46] [47]
20	Kundan Kumar	[43]
21	M. Tilak Kumar	[34] [48] [49]
22	S. Krishna Kumar	[42] [44] [46] [47] [54]
23	Santanu Kundu	[33] [38] [43] [51]
24	Subhadip Kundu	[42] [45] [46] [50] [54] [55]
25	Tapas K. Maiti	[35]
26	Pradip Mandal	[44]
27	Kanchan Manna	[43]
28	S. Mitra	[6]
29	Joy Mukherjee	[17]
30	Prasanta Kumar Nandi	[12]
31	S. Nandi	[5]
32	Ajit Pal	[41]
33	Rohit Pandey	[19]
34	Ritesh Parikh	[43]
35	Kolin Paul	[12]
36	Sambhu Nath Pradhan	[34] [48] [49]
37	M. Deb Purkayastha	[12]
38	B. Mallikarjuna Rao	[31]
39	J. Srinivasa Rao	[27] [39]
40	K. Sudarsana Reddy	[21]
41	A. Roy	[12]
42	B. N. Roy	[12]
43	Samir Roy	[1] [4] [7]
44	Pradip Kumar Sahu	[53]
45	Dipankar Sarkar	[23]
46	Soumojit Sarkar	[28] [30]
47	Jakki Sasidhar	[22]
48	Koppolu Sasidhar	[3]
49	D. Satyanarayana	[22]
50	Indranil Sengupta	[13] [14] [15] [16] [50] [55]
51	Rafiahamed Shaik	[36]
52	Naresh Shenoy	[37]
53	Krishna Teja Sistla	[40]
54	Dilip Kumar Reddy Tipparthi	[32]
55	Tarang Vaish	[26]
56	Putta Venkatesh	[52] [53]

Colors in the list of coauthors

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