 | 2012 |
|---|
| 7 |       | Atanu Chattopadhyay,
Zeljko Zilic:
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks.
IEEE Trans. VLSI Syst. 20(3): 523-536 (2012) |
| 2009 |
|---|
| 6 | | Atanu Chattopadhyay,
Zeljko Zilic:
Serial reconfigurable mismatch-tolerant clock distribution.
DAC 2009: 611-612 |
| 2008 |
|---|
| 5 | | Atanu Chattopadhyay,
Zeljko Zilic:
Built-in Clock Skew System for On-line Debug and Repair.
DATE 2008: 248-251 |
| 2007 |
|---|
| 4 | | Atanu Chattopadhyay,
Zeljko Zilic:
Reconfigurable Clock Distribution Circuitry.
ISCAS 2007: 877-880 |
| 2005 |
|---|
| 3 | | Jean-Samuel Chenard,
Ahmed Usman Khalid,
Milos Prokic,
Rong Zhang,
K.-L. Lim,
Atanu Chattopadhyay,
Zeljko Zilic:
Expandable and Robust Laboratory for Microprocessor Systems.
MSE 2005: 65-66 |
| 2 | | Atanu Chattopadhyay,
Zeljko Zilic:
GALDS: a complete framework for designing multiclock ASICs and SoCs.
IEEE Trans. VLSI Syst. 13(6): 641-654 (2005) |
| 2003 |
|---|
| 1 | | Atanu Chattopadhyay,
Zeljko Zilic:
A globally asynchronous locally dynamic system for ASICs and SoCs.
ACM Great Lakes Symposium on VLSI 2003: 176-181 |
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