Satrajit Chatterjee

	2012
17		Satrajit Chatterjee, Michael Kishinevsky: Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics. Formal Methods in System Design 40(2): 147-169 (2012)
	2011
16		Chen-Ling Chou, Radu Marculescu, Ümit Y. Ogras, Satrajit Chatterjee, Michael Kishinevsky, Dmitrii Loukianov: System interconnect design exploration for embedded MPSoCs. SLIP 2011: 1-8
15		Alexander Gotmanov, Satrajit Chatterjee, Michael Kishinevsky: Verifying Deadlock-Freedom of Communication Fabrics. VMCAI 2011: 214-231
	2010
14		Satrajit Chatterjee, Michael Kishinevsky: Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics. CAV 2010: 321-338
13		Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras: Quick formal modeling of communication fabrics to enable verification. HLDVT 2010: 42-49
12		Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Michael Kishinevsky, Ümit Y. Ogras: Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. NOCS 2010: 125-134
	2008
11		Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee: Boolean factoring and decomposition of logic networks. ICCAD 2008: 38-44
	2007
10		Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann: On Resolution Proofs for Combinational Equivalence. DAC 2007: 600-605
9		Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton: Combinational and sequential mapping with priority cuts. ICCAD 2007: 354-361
8		Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 240-253 (2007)
	2006
7		Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC 2006: 532-535
6		Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: Improvements to technology mapping for LUT-based FPGAs. FPGA 2006: 41-49
5		Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton: Factor cuts. ICCAD 2006: 143-150
4		Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén: Improvements to combinational equivalence checking. ICCAD 2006: 836-843
3		Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam: Reducing Structural Bias in Technology Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2894-2903 (2006)
	2005
2		Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam: Reducing structural bias in technology mapping. ICCAD 2005: 519-526
	2004
1		Satrajit Chatterjee, Robert K. Brayton: A new incremental placement algorithm and its application to congestion-aware divisor extraction. ICCAD 2004: 541-548

Coauthor Index

1	Robert K. Brayton	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
2	Sungmin Cho	[9]
3	Chen-Ling Chou	[16]
4	Jordi Cortadella	[12]
5	Niklas Eén	[4]
6	Alexander Gotmanov	[15]
7	Timothy Kam	[2] [3]
8	Michael Kishinevsky	[12] [13] [14] [15] [16] [17]
9	Andreas Kuehlmann	[10]
10	Dmitrii Loukianov	[16]
11	Radu Marculescu	[16]
12	Alan Mishchenko	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
13	Nikita Nikitin	[12]
14	Ümit Y. Ogras	[12] [13] [16]
15	Xinning Wang	[2] [3]

Last update Tue May 29 01:28:40 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page