Karam S. Chatha

	2011
63		Weijia Che, Karam S. Chatha: Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming. DAC 2011: 122-127
62		Weijia Che, Karam S. Chatha: Scheduling of stream programs onto SPM enhanced processors with code overlay. ESTImedia 2011: 9-18
61		Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha: Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1677-1690 (2011)
	2010
60		Weijia Che, Karam S. Chatha: Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine. ASAP 2010: 21-28
59		Glenn Leary, Karam S. Chatha: A holistic approach to network-on-chip synthesis. CODES+ISSS 2010: 213-222
58		Michael A. Baker, Amrit Panda, Nikhil Ghadge, Aniruddha Kadne, Karam S. Chatha: A performance model and code overlay generator for scratchpad enhanced embedded processors. CODES+ISSS 2010: 287-296
57		Sushu Zhang, Karam S. Chatha: Thermal aware task sequencing on embedded processors. DAC 2010: 585-590
56		Weijia Che, Amrit Panda, Karam S. Chatha: Compilation of stream programs for multicore processors that incorporate scratchpad memories. DATE 2010: 1118-1123
55		Weijia Che, Karam S. Chatha: Scheduling of synchronous data flow models on scratchpad memory based embedded processors. ICCAD 2010: 205-212
54		Michael A. Baker, Karam S. Chatha: A lightweight run-time scheduler for multitasking multicore stream applications. ICCD 2010: 297-304
53		Glenn Leary, Karam S. Chatha: Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance. VLSI Design 2010: 200-205
	2009
52		Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula: A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS 2009: 353-362
51		Glenn Leary, Karam S. Chatha: Automated technique for design of NoC with minimal communication latency. CODES+ISSS 2009: 471-480
50		Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha: Throughput optimal task allocation under thermal constraints for multi-core processors. DAC 2009: 776-781
49		Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha: Performance optimal speed control of multi-core processors under thermal constraints. DATE 2009: 1548-1551
48		Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha: Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. ICCAD 2009: 310-313
47		Sushu Zhang, Karam S. Chatha, Goran Konjevod: Near optimal battery-aware energy management. ISLPED 2009: 249-254
46		Saraju P. Mohanty, Nasir Memon, Karam S. Chatha: Circuits and systems for real-time security and copyright protection of multimedia. Computers & Electrical Engineering 35(2): 231-234 (2009)
45		Glenn Leary, Krishnan Srinivasan, Krishna Mehta, Karam S. Chatha: Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique. IEEE Trans. VLSI Syst. 17(5): 674-687 (2009)
	2008
44		Sushu Zhang, Karam S. Chatha: Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures. ASP-DAC 2008: 61-66
43		Michael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li: Power reduction via macroblock prioritization for power aware H.264 video applications. CODES+ISSS 2008: 261-266
42		Sushu Zhang, Karam S. Chatha: System-level thermal aware design of applications with uncertain execution time. ICCAD 2008: 242-249
41		Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod: Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1425-1438 (2008)
	2007
40		Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod: Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. ASP-DAC 2007: 184-190
39		Christopher Ostler, Karam S. Chatha, Goran Konjevod: Approximation Algorithm for Process Mapping on Network Processor Architectures. ASP-DAC 2007: 577-582
38		Glenn Leary, Krishna Mehta, Karam S. Chatha: Performance and resource optimization of NoC router architecture for master and slave IP cores. CODES+ISSS 2007: 155-160
37		Michael A. Baker, Aviral Shrivastava, Karam S. Chatha: Smart driver for power reduction in next generation bistable electrophoretic display technology. CODES+ISSS 2007: 197-202
36		Christopher Ostler, Karam S. Chatha: Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures. DAC 2007: 801-804
35		Christopher Ostler, Karam S. Chatha: An ILP formulation for system-level application mapping on network processor architectures. DATE 2007: 99-104
34		Sushu Zhang, Karam S. Chatha: Approximation algorithm for the temperature-aware scheduling problem. ICCAD 2007: 281-288
33		Sushu Zhang, Karam S. Chatha, Goran Konjevod: Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. ISLPED 2007: 225-230
32		Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan: ILP and heuristic techniques for system-level design on network processor architectures. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
31		Krishnan Srinivasan, Karam S. Chatha: Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints. Integration 40(3): 326-354 (2007)
30		Lina Peng, K. Selçuk Candan, Christopher B. Mayer, Karam S. Chatha, Kyung Dong Ryu: Optimization of media processing workflows with adaptive operator behaviors. Multimedia Tools Appl. 33(3): 245-272 (2007)
	2006
29		Lina Peng, Gisik Kwon, Yinpeng Chen, K. Selçuk Candan, Hari Sundaram, Karam S. Chatha, Maria Luisa Sapino: Modular Design of Media Retrieval Workflows Using ARIA. CIVR 2006: 491-494
28		Krishnan Srinivasan, Karam S. Chatha: Layout aware design of mesh based NoC architectures. CODES+ISSS 2006: 136-141
27		Krishnan Srinivasan, Karam S. Chatha: A low complexity heuristic for design of custom network-on-chip architectures. DATE 2006: 130-135
26		Krishnan Srinivasan, Karam S. Chatha: A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. ISQED 2006: 352-357
25		Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod: Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans. VLSI Syst. 14(4): 407-420 (2006)
	2005
24		Lina Peng, Gisik Kwon, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram, Yinpeng Chen: Media processing workflow design and execution with ARIA. ACM Multimedia 2005: 800-801
23		Krishnan Srinivasan, Karam S. Chatha: SAGA: synthesis technique for guaranteed throughput NoC architectures. ASP-DAC 2005: 489-494
22		Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod: An automated technique for topology and route generation of application specific on-chip interconnection networks. ICCAD 2005: 231-237
21		Krishnan Srinivasan, Karam S. Chatha: A technique for low energy mapping and routing in network-on-chip architectures. ISLPED 2005: 387-392
20		Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha: System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. ISVLSI 2005: 110-116
19		Nagendran Rangan, Karam S. Chatha: A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. VLSI Design 2005: 564-569
18		Krishnan Srinivasan, Karam S. Chatha: ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. VLSI Design 2005: 623-628
17		Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha: Quality-of-service and error control techniques for mesh-based network-on-chip architectures. Integration 38(3): 353-382 (2005)
	2004
16		Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha: Quality-of-service and error control techniques for network-on-chip architectures. ACM Great Lakes Symposium on VLSI 2004: 45-50
15		Lina Peng, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram: ARIA: an adaptive and programmable media-flow architecture for interactive arts. ACM Multimedia 2004: 532-535
14		Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha: A Power and Performance Model for Network-on-Chip Architectures. DATE 2004: 1250-1255
13		Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod: Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. ICCD 2004: 422-429
12		Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha: A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. ISVLSI 2004: 313-316
11		Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha: System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. ISVLSI 2004: 39-45
10		K. Selçuk Candan, Lina Peng, Kyung Dong Ryu, Karam S. Chatha, Christopher B. Mayer: Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures. Multimedia Information Systems 2004: 30-39
9		Krishnan Srinivasan, Karam S. Chatha: An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. VLSI Design 2004: 255-260
	2002
8		Karam S. Chatha, Ranga Vemuri: Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Trans. VLSI Syst. 10(3): 193-208 (2002)
	2001
7		Karam S. Chatha, Ranga Vemuri: MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. CODES 2001: 42-47
	2000
6		Karam S. Chatha, Ranga Vemuri: An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling. Design Autom. for Emb. Sys. 5(3-4): 281-293 (2000)
	1999
5		Karam S. Chatha, Ranga Vemuri: Hardware-Software Codesign for Dynamically Reconfigurable Architectures. FPL 1999: 175-184
4		Karam S. Chatha, Ranga Vemuri: An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. IEEE International Workshop on Rapid System Prototyping 1999: 134-139
	1998
3		Karam S. Chatha, Ranga Vemuri: RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. CODES 1998: 139-143
2		Karam S. Chatha, Ranga Vemuri: A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. ISSS 1998: 145-151
1		Karam S. Chatha, Ranga Vemuri: Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. International Workshop on Rapid System Prototyping 1998: 218-224

Coauthor Index

1	Michael A. Baker	[37] [43] [52] [54] [58]
2	Nilanjan Banerjee	[14] [16] [17]
3	K. Selçuk Candan (Kasim Selçuk Candan)	[10] [15] [24] [29] [30]
4	Weijia Che	[55] [56] [60] [62] [63]
5	Yinpeng Chen	[24] [29]
6	Pravin Dalale	[52]
7	Nikhil Ghadge	[58]
8	Vinay Hanumaiah	[48] [49] [50] [61]
9	Aniruddha Kadne	[58]
10	Goran Konjevod	[13] [22] [25] [33] [39] [40] [41] [47]
11	Gisik Kwon	[24] [29]
12	Glenn Leary	[38] [45] [51] [53] [59]
13	Baoxin Li	[43]
14	Christopher B. Mayer	[10] [30]
15	Jason McCollum	[20]
16	Krishna Mehta	[38] [45]
17	Nasir Memon	[46]
18	Saraju P. Mohanty	[46]
19	Christopher Ostler	[20] [32] [35] [36] [39]
20	Amrit Panda	[56] [58]
21	Viswesh Parameswaran	[43]
22	Lina Peng	[10] [15] [24] [29] [30]
23	Vijay Ramamurthi	[11] [12] [32]
24	Vijaykumar Ramamurthi	[20]
25	Nagendran Rangan	[19]
26	Ravishankar Rao	[50]
27	Kyung Dong Ryu	[10] [15] [24] [30]
28	Maria Luisa Sapino	[29]
29	Aviral Shrivastava	[37]
30	Krishnan Srinivasan	[9] [11] [12] [13] [18] [21] [22] [23] [25] [26] [27] [28] [31] [32] [40] [41] [45]
31	Hari Sundaram	[15] [24] [29]
32	Nagender Telkar	[11]
33	Praveen Vellanki	[14] [16] [17]
34	Ranga Vemuri	[1] [2] [3] [4] [5] [6] [7] [8]
35	Sarma B. K. Vrudhula	[48] [49] [50] [52] [61]
36	Sushu Zhang	[33] [34] [42] [44] [47] [57]

Colors in the list of coauthors

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