Biswadeep Chaterjee

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2000

1 B. Suresh, Biswadeep Chaterjee, R. Harinath: Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. VLSI Design 2000: 512-517

	2000
1		B. Suresh, Biswadeep Chaterjee, R. Harinath: Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. VLSI Design 2000: 512-517

Coauthor Index

1 R. Harinath [1]

2 B. Suresh [1]

Last update Tue May 29 01:28:40 2012 CET by the DBLP Team —

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