Shweta Chary

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2006

2 Shweta Chary, Michael L. Bushnell: Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 413-418

1 Shweta Chary, Michael L. Bushnell: Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 818-823

	2006
2		Shweta Chary, Michael L. Bushnell: Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 413-418
1		Shweta Chary, Michael L. Bushnell: Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 818-823

Coauthor Index

1 Michael L. Bushnell [1] [2]

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