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| 2006 | ||
|---|---|---|
| 1 | Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang: Simultaneous block and I/O buffer floorplanning for flip-chip design. ASP-DAC 2006: 213-218 | |
| 1 | Yao-Wen Chang | [1] |
| 2 | Chih-Yang Peng | [1] |
| 3 | Jyh-Herng Wang | [1] |
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