Ting-Sheng Chao

	2010
3		Wei-Bin Yang, Yu-lung Lo, Ting-Sheng Chao: A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output. IEICE Transactions 93-C(3): 309-316 (2010)
	2009
2		Yu-lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng: Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. on Circuits and Systems 56-II(5): 339-343 (2009)
1		Yu-lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng: High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Transactions 92-C(6): 890-893 (2009)

Coauthor Index

1	Kuo-Hsing Cheng	[1] [2]
2	Yu-lung Lo	[1] [2] [3]
3	Wei-Bin Yang	[1] [2] [3]

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