Yun-Nan Chang

	2010
14		Yun-Nan Chang: A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver. IEEE Trans. VLSI Syst. 18(5): 840-843 (2010)
13		Yun-Nan Chang: Digit-Serial Pipeline Sorter Architecture. Signal Processing Systems 61(2): 241-249 (2010)
	2009
12		Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang: An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. ASP-DAC 2009: 131-132
11		Yun-Nan Chang, Ting-Chi Tong: A Lossless Buffer Compression Scheme for 3D Graphic System. CGVR 2009: 116-121
10		Yun-Nan Chang: A Fast Spline Curve Rendering Accelerator Architecture. IEEE Trans. on Circuits and Systems 56-II(11): 870-874 (2009)
	2008
9		Yun-Nan Chang: An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design. IEEE Trans. on Circuits and Systems 55-II(12): 1234-1238 (2008)
8		Yun-Nan Chang, Ting-Chi Tong: An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization. Signal Processing Systems 53(3): 435-448 (2008)
	2005
7		Yun-Nan Chang: Design of an efficient memory-based DVB-T channel decoder. ISCAS (5) 2005: 5019-5022
	2003
6		Yun-Nan Chang: Design of soft-output Viterbi decoders with hybrid trace-back processing. ISCAS (2) 2003: 69-72
5		Yun-Nan Chang: An Efficient In-Place VLSI Architecture for Viterbi Algorithm. VLSI Signal Processing 33(3): 317-324 (2003)
	1998
4		Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi: Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units. VLSI Signal Processing 19(3): 243-256 (1998)
	1997
3		Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi: Design and Implementation of Low-Power Digit-Serial Multipliers. ICCD 1997: 186-195
	1996
2		Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi: Loop-List Scheduling for Heterogeneous Functional Units. Great Lakes Symposium on VLSI 1996: 2-7
1		Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang: Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. ICCD 1996: 492-499

Coauthor Index

1	Liang-Bi Chen	[12]
2	Ruei-Ting Gu	[12]
3	Tsung-Yu Ho	[12]
4	Shen-Fu Hsiao	[12]
5	Ing-Jer Huang	[12]
6	Wei-Sheng Huang	[12]
7	Chung-Nan Lee	[12]
8	Keshab K. Parhi	[1] [2] [3] [4]
9	Janardhan H. Satyanarayana	[1] [3]
10	Wen-Chi Shiue	[12]
11	Leilei Song	[1]
12	Ting-Chi Tong	[8] [11]
13	Chien-Chou Wang	[12]
14	Ching-Yi Wang	[2] [4]

Colors in the list of coauthors

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