Ying-Tsai Chang

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2006

4 Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang: Visibility enhancement for silicon debug. DAC 2006: 13-18

2004

3 Ying-Tsai Chang, Kwang-Ting Cheng: Self-referential verification for gate-level implementations of arithmetic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1102-1112 (2004)

2002

2 Ying-Tsai Chang, Kwang-Ting Cheng: Self-referential verification of gate-level implementations of arithmetic circuits. DAC 2002: 311-316

2001

1 Ying-Tsai Chang, Kwang-Ting Cheng: Induction-Based Gate-Level Verification of Multipliers. ICCAD 2001: 190-

	2006
4		Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang: Visibility enhancement for silicon debug. DAC 2006: 13-18
	2004
3		Ying-Tsai Chang, Kwang-Ting Cheng: Self-referential verification for gate-level implementations of arithmetic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1102-1112 (2004)
	2002
2		Ying-Tsai Chang, Kwang-Ting Cheng: Self-referential verification of gate-level implementations of arithmetic circuits. DAC 2002: 311-316
	2001
1		Ying-Tsai Chang, Kwang-Ting Cheng: Induction-Based Gate-Level Verification of Multipliers. ICCAD 2001: 190-

Coauthor Index

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team —

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1	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[1] [2] [3]
2	Yu-Chin Hsu	[4]
3	Wells Jong	[4]
4	Fur-Shing Tsai	[4]