 | 2010 |
| 10 |  | Yu-Shih Su,
Wing-Kai Hon,
Cheng-Chih Yang,
Shih-Chieh Chang,
Yeong-Jar Chang:
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1921-1930 (2010) |
| 2009 |
| 9 |  | Yu-Shih Su,
Wing-Kai Hon,
Cheng-Chih Yang,
Shih-Chieh Chang,
Yeong-Jar Chang:
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
ICCAD 2009: 535-538 |
| 8 |  | Ming-Dou Ker,
Po-Yen Chiu,
Fu-Yi Tsai,
Yeong-Jar Chang:
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.
ISCAS 2009: 2281-2284 |
| 2008 |
| 7 |  | Chung-Fu Lin,
Chia-Fu Huang,
De-Chung Lu,
Chih-Chiang Hsu,
Wen-Tsung Chiu,
Yu-Wei Chen,
Yeong-Jar Chang:
A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances.
ITC 2008: 1 |
| 2005 |
| 6 |  | Ming Shae Wu,
Chung-Len Lee,
Yeong-Jar Chang,
Wen Ching Wu:
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.
Asian Test Symposium 2005: 106-111 |
| 2004 |
| 5 |  | Rei-Fu Huang,
Chin-Lung Su,
Cheng-Wen Wu,
Shen-Tien Lin,
Kun-Lun Luo,
Yeong-Jar Chang:
Fail Pattern Identification for Memory Built-In Self-Repair.
Asian Test Symposium 2004: 366-371 |
| 4 |  | Chin-Lung Su,
Rei-Fu Huang,
Cheng-Wen Wu,
Chien-Chung Hung,
Ming-Jer Kao,
Yeong-Jar Chang,
Wen Ching Wu:
MRAM Defect Analysis and Fault Modeli.
ITC 2004: 124-133 |
| 3 |  | Li-Ming Denq,
Rei-Fu Huang,
Cheng-Wen Wu,
Yeong-Jar Chang,
Wen Ching Wu:
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.
MTDT 2004: 65-69 |
| 2000 |
| 2 |  | Yeong-Jar Chang,
Chung-Len Lee,
Jwu E. Chen,
Chauchin Su:
A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier.
J. Inf. Sci. Eng. 16(5): 751-766 (2000) |
| 1994 |
| 1 |  | Yeong-Jar Chang,
Chung-Len Lee:
Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic.
ISMVL 1994: 35-41 |