Yao-Wen Chang

	2012
189		Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang: Statistical thermal modeling and optimization considering leakage power variations. DATE 2012: 605-610
188		Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang: Graph-based subfield scheduling for electron-beam photomask fabrication. ISPD 2012: 9-16
187		Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang: Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 703-716 (2012)
186		Chung-Wei Lin, Po-Wei Lee, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng: An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(6): 878-889 (2012)
	2011
185		Yao-Wen Chang, Jiang Hu: Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011 ACM 2011
184		Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang: Simultaneous functional and timing ECO. DAC 2011: 140-145
183		Meng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov: TSV-aware analytical placement for 3D IC designs. DAC 2011: 664-669
182		Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang: Escape routing for staggered-pin-array PCBs. ICCAD 2011: 306-309
181		Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu: A corner stitching compliant B∗-tree representation and its applications to analog placement. ICCAD 2011: 507-511
180		Pang-Yen Chou, Hung-Chih Ou, Yao-Wen Chang: Heterogeneous B∗-trees for analog placement with symmetry and regularity considerations. ICCAD 2011: 512-516
179		Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang: Timing ECO optimization via Bézier curve smoothing and fixability identification. ICCAD 2011: 742-746
178		Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang: Routability-driven analytical placement for mixed-size circuit designs. ICCAD 2011: 80-84
177		Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu: PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. ICCAD 2011: 85-90
176		Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang: A SAT-based routing algorithm for cross-referencing biochips. SLIP 2011: 1-7
175		Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang: Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1649-1662 (2011)
174		Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang: Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(12): 1856-1869 (2011)
173		Prashant Saxena, Yao-Wen Chang: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 165-166 (2011)
172		Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif: Simultaneous Layout Migration and Decomposition for Double Patterning Technology. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 284-294 (2011)
171		Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang: Thermal-Driven Analog Placement Considering Device Matching. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 325-336 (2011)
170		Cliff Chiung-Yu Lin, Yao-Wen Chang: Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 817-828 (2011)
	2010
169		Prashant Saxena, Yao-Wen Chang: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010 ACM 2010
168		Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang: Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. ASP-DAC 2010: 169-174
167		Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang: TRECO: dynamic technology remapping for timing engineering change orders. ASP-DAC 2010: 331-336
166		Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang: Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. ASP-DAC 2010: 395-400
165		Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang: Pulsed-latch aware placement for timing-integrity optimization. DAC 2010: 280-285
164		Cliff Chiung-Yu Lin, Yao-Wen Chang: Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips. DAC 2010: 641-646
163		Xin-Wei Shih, Yao-Wen Chang: Fast timing-model independent buffered clock-tree synthesis. DAC 2010: 80-85
162		Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif: Template-mask design methodology for double patterning technology. ICCAD 2010: 107-111
161		Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang: Redundant-wires-aware ECO timing and mask cost optimization. ICCAD 2010: 381-386
160		Hsu-Chieh Lee, Yao-Wen Chang, Po-Wei Lee: Recent research development in flip-chip routing. ICCAD 2010: 404-410
159		Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang: High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. ICCAD 2010: 452-457
158		Szu-Yu Chen, Yao-Wen Chang: Native-conflict-aware wire perturbation for double patterning technology. ICCAD 2010: 556-561
157		Meng-Kai Hsu, Yao-Wen Chang: Unified analytical global placement for large-scale mixed-size circuit designs. ICCAD 2010: 657-662
156		Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan: Design-hierarchy aware mixed-size placement for routability optimization. ICCAD 2010: 663-668
155		Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang: Efficient provably good OPC modeling and its applications to interconnect optimization. ICCD 2010: 336-341
154		Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang: Density gradient minimization with coupling-constrained dummy fill for CMP control. ISPD 2010: 105-111
153		Jaw-Luen Tang, Yao-Wen Chang: Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications. EURASIP J. Wireless Comm. and Networking 2010: (2010)
152		Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang: Predictive Formulae for OPC With Applications to Lithography-Friendly Routing. IEEE Trans. on CAD of Integrated Circuits and Systems 29(1): 40-50 (2010)
151		Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang: Multilayer Global Routing With Via and Wire Capacity Considerations. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 685-696 (2010)
150		Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang: ECO Timing Optimization Using Spare Cells and Technology Remapping. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 697-710 (2010)
149		Jia-Wei Fang, Yao-Wen Chang: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 711-721 (2010)
148		Cliff Chiung-Yu Lin, Yao-Wen Chang: ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1315-1327 (2010)
	2009
147		Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang: High-performance global routing with fast overflow reduction. ASP-DAC 2009: 582-587
146		Cliff Chiung-Yu Lin, Yao-Wen Chang: ILP-based pin-count aware design methodology for microfluidic biochips. DAC 2009: 258-263
145		Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang: Flip-chip routing with unified area-I/O pad assignments for package-board co-design. DAC 2009: 336-339
144		Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao: Spare-cell-aware multilevel analytical placement. DAC 2009: 430-435
143		Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang: Thermal-driven analog placement considering device matching. DAC 2009: 593-598
142		Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng: BIST design optimization for large-scale embedded memory cores. ICCAD 2009: 197-200
141		Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng: An efficient pre-assignment routing algorithm for flip-chip designs. ICCAD 2009: 239-244
140		Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif: Simultaneous layout migration and decomposition for double patterning technology. ICCAD 2009: 595-600
139		Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang: Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. ICCAD 2009: 666-673
138		Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang: Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. ISPD 2009: 5-12
137		Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: T-trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Design Autom. Electr. Syst. 14(4): (2009)
136		Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang: An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 98-110 (2009)
135		Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang: A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 193-206 (2009)
134		Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang: Voltage-Island Partitioning and Floorplanning Under Timing Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 690-702 (2009)
133		Mark Po-Hung Lin, Yao-Wen Chang, Shyh-Chang Lin: Analog Placement Based on Symmetry-Island Formulation. IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 791-804 (2009)
132		Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1295-1306 (2009)
	2008
131		Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang: Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. DAC 2008: 167-172
130		Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289
129		Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang: Predictive formulae for OPC with applications to lithography-friendly routing. DAC 2008: 510-515
128		Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang: Constraint graph-based macro placement for modern mixed-size circuit designs. ICCAD 2008: 218-223
127		Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang: Multi-layer global routing considering via and wire capacities. ICCAD 2008: 350-355
126		Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang: Routing for chip-package-board co-design considering differential pairs. ICCAD 2008: 512-517
125		Jia-Wei Fang, Yao-Wen Chang: Area-I/O flip-chip routing for chip-package co-design. ICCAD 2008: 518-522
124		Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38
123		Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1928-1941 (2008)
122		Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang: Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2007-2016 (2008)
121		Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2145-2155 (2008)
120		Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin: A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 286-294 (2008)
119		Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang: Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 643-653 (2008)
118		Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: Effective Wire Models for X-Architecture Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 654-658 (2008)
117		Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han: Full-Chip Routing Considering Double-Via Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 844-857 (2008)
116		Zhe-Wei Jiang, Yao-Wen Chang: An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1055-1065 (2008)
115		Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1228-1240 (2008)
114		Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen: An Efficient Graph-Based Algorithm for ESD Current Path Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1363-1375 (2008)
113		Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu: MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1621-1634 (2008)
	2007
112		Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang: Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC 2007: 238-243
111		Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu: MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. DAC 2007: 447-452
110		Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang: An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. DAC 2007: 606-611
109		Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang: A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. DAC 2007: 887-890
108		I-Jye Lin, Yao-Wen Chang: An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. ICCAD 2007: 119-124
107		Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang: Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. ICCAD 2007: 380-385
106		Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang: ECO timing optimization using spare cells. ICCAD 2007: 530-535
105		Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang: An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. ICCAD 2007: 650-655
104		Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD 2007: 752-757
103		Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang: Novel wire density driven full-chip routing for CMP variation control. ICCAD 2007: 831-838
102		Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen: 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME 2007: 9
101		Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED 2007: 92-97
100		Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang: Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD 2007: 127-134
99		Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: X-architecture placement based on effective wire models. ISPD 2007: 87-94
98		Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang: A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. PATMOS 2007: 148-159
97		I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang: Statistical circuit optimization considering device andinterconnect process variations. SLIP 2007: 47-54
96		Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
95		Bor-Yiing Su, Yao-Wen Chang: An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1818-1829 (2007)
94		Chen-Wei Liu, Yao-Wen Chang: Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 693-704 (2007)
93		Bor-Yiing Su, Yao-Wen Chang, Jiang Hu: An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 719-733 (2007)
92		Tai-Chen Chen, Yao-Wen Chang: Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1041-1053 (2007)
91		Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, Jyh-Herng Wang: A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1417-1429 (2007)
90		Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang: MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1430-1444 (2007)
89		Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1625-1636 (2007)
88		Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. JETC 3(3): (2007)
	2006
87		Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang: Simultaneous block and I/O buffer floorplanning for flip-chip design. ASP-DAC 2006: 213-218
86		Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen: IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371
85		Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin: A novel framework for multilevel full-chip gridless routing. ASP-DAC 2006: 636-641
84		Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han: Novel full-chip gridless routing considering double-via insertion. DAC 2006: 755-760
83		Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of digital microfluidic biochips using the t-tree formulation. DAC 2006: 931-934
82		Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ICCAD 2006: 187-192
81		Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang: Voltage island aware floorplanning for power and timing optimization. ICCAD 2006: 389-394
80		Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo: Current path analysis for electrostatic discharge protection. ICCAD 2006: 510-515
79		Zhe-Wei Jiang, Yao-Wen Chang: An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. ICCAD 2006: 669-674
78		Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai: Inductance extraction for general interconnect structures. ISCAS 2006
77		Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: NTUplace2: a hybrid placer using partitioning and analytical techniques. ISPD 2006: 215-217
76		Bor-Yiing Su, Yao-Wen Chang, Jiang Hu: An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD 2006: 56-63
75		Chen-Wei Liu, Yao-Wen Chang: Floorplan and power/ground network co-synthesis for fast design convergence. ISPD 2006: 86-93
74		Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou: Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006)
73		Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou: RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2258-2264 (2006)
72		Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen: IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2513-2525 (2006)
71		Tung-Chieh Chen, Yao-Wen Chang: Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 637-650 (2006)
70		Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with jumper insertion for antenna avoidance. Integration 39(4): 420-432 (2006)
	2005
69		Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang: Placement with symmetry constraints for analog layout design using TCG-S. ASP-DAC 2005: 1135-1137
68		Tai-Chen Chen, Yao-Wen Chang: Multilevel full-chip gridless routing considering optical proximity correction. ASP-DAC 2005: 1160-1163
67		Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang: SoC test scheduling using the B-tree based floorplanning technique. ASP-DAC 2005: 1188-1191
66		Bor-Yiing Su, Yao-Wen Chang: An exact jumper insertion algorithm for antenna effect avoidance/fixing. DAC 2005: 325-328
65		Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen: Multilevel full-chip routing for the X-based architecture. DAC 2005: 597-602
64		Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin: IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. ICCAD 2005: 159-164
63		Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang: A routing algorithm for flip-chip design. ICCAD 2005: 753-758
62		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) 2005: 4134-4137
61		Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang: Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED 2005: 123-126
60		Tung-Chieh Chen, Yao-Wen Chang: Modern floorplanning based on fast simulated annealing. ISPD 2005: 104-112
59		Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang: NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. ISPD 2005: 236-238
58		Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen: Reconfigurable Platform for Content Science Research. RTCSA 2005: 481-486
57		Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen: Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36
56		Jai-Ming Lin, Yao-Wen Chang: TCG: A transitive closure graph-based representation for general floorplans. IEEE Trans. VLSI Syst. 13(2): 288-292 (2005)
55		Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee: Crosstalk- and performance-driven multilevel full-chip routing. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 869-878 (2005)
	2004
54		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273
53		Yi-Hui Cheng, Yao-Wen Chang: Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. ASP-DAC 2004: 624-627
52		Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen: Temporal floorplanning using 3D-subTCG. ASP-DAC 2004: 725-730
51		Su-Wei Wu, Yao-Wen Chang: Efficient power/ground network analysis for power integrity-driven design methodology. DAC 2004: 177-180
50		Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the T-tree formulation. ICCAD 2004: 300-305
49		Meng-Chen Wu, Yao-Wen Chang: Placement with Alignment and Performance Constraints Using the B*-Tree Representation. ICCD 2004: 568-571
48		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) 2004: 945-948
47		Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with antenna avoidance. ISPD 2004: 34-40
46		Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang: Timing modeling and optimization under the transmission line model. IEEE Trans. VLSI Syst. 12(1): 28-41 (2004)
45		Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao: Simultaneous floor plan and buffer-block optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004)
44		Yao-Wen Chang, Shih-Ping Lin: MR: a new framework for multilevel full-chip routing. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 793-800 (2004)
43		Jai-Ming Lin, Yao-Wen Chang: TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 968-980 (2004)
42		Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang: A clustering- and probability-based approach for time-multiplexed FPGA partitioning. Integration 38(2): 245-265 (2004)
	2003
41		Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang: Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC 2003: 812-817
40		Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee: A Fast Crosstalk- and Performance-Driven Multilevel Routing System. ICCAD 2003: 382-387
39		Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong: Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. 8(1): 11-37 (2003)
38		Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang: Rectilinear block placement using B*-trees. ACM Trans. Design Autom. Electr. Syst. 8(2): 188-202 (2003)
37		Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin: Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. IEEE Trans. VLSI Syst. 11(4): 679-686 (2003)
	2002
36		Jai-Ming Lin, Yao-Wen Chang: TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. DAC 2002: 842-847
35		Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang: Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. DATE 2002: 69-75
34		Shih-Ping Lin, Yao-Wen Chang: A novel framework for multilevel routing considering routability and performance. ICCAD 2002: 44-50
33		Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang: Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ISQED 2002: 523-528
32		Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang: Performance-driven placement for dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 628-642 (2002)
31		Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang: Comment on Generic Universal Switch Blocks. IEEE Trans. Computers 51(1): 93-96 (2002)
30		Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang: Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. IEEE Trans. VLSI Syst. 10(6): 886-901 (2002)
	2001
29		Jai-Ming Lin, Yao-Wen Chang: TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. DAC 2001: 764-769
28		Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang: Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. ICCD 2001: 192-198
27		Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang: Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. ICCD 2001: 335-347
26		Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang: An Algorithm for Dynamically Reconfigurable FPGA Placement. ICCD 2001: 501-504
25		Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang: Generic ILP-based approaches for time-multiplexed FPGA partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1266-1274 (2001)
24		Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong: Matching-based algorithm for FPGA channel segmentation design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 784-791 (2001)
	2000
23		Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu: B*-Trees: a new representation for non-slicing floorplans. DAC 2000: 458-463
22		Yao-Wen Chang, Yu-Tsang Chang: An architecture-driven metric for simultaneous placement and global routing for FPGAs. DAC 2000: 567-572
21		Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang: Rectilinear Block Placement Using B*-Trees. ICCD 2000: 351-356
20		Song-Ra Pan, Yao-Wen Chang: Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. ICCD 2000: 581-584
19		Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou: Optimal reliable crosstalk-driven interconnect optimization. ISPD 2000: 128-133
18		Yao-Wen Chang, Kai Zhu, D. F. Wong: Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 5(3): 433-450 (2000)
17		Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang: Generic Universal Switch Blocks. IEEE Trans. Computers 49(4): 348-359 (2000)
16		Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou: Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 999-1010 (2000)
	1999
15		Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang: Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC 1999: 90-95
14		Guang-Ming Wu, Michael Shyu, Yao-Wen Chang: Universal Switch Blocks for Three-Dimensional FPGA Design. FPGA 1999: 254
13		Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang: A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD 1999: 364-369
12		Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang: Generic Universal Switch Blocks. ICCD 1999: 311-314
11		Guang-Ming Wu, Yao-Wen Chang: Quasi-Universal Switch Matrices for FPD Design. IEEE Trans. Computers 48(10): 1107-1122 (1999)
	1998
10		Yao-Wen Chang, Jai-Ming Lin, D. F. Wong: Graph matching-based algorithms for FPGA segmentation design. ICCAD 1998: 34-39
9		Guang-Ming Wu, Yao-Wen Chang: Switch-matrix architecture and routing for FPDs. ISPD 1998: 158-163
	1997
8		Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan: Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 32-46 (1997)
	1996
7		Chung-Ping Chen, Yao-Wen Chang, D. F. Wong: Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC 1996: 405-408
6		Yao-Wen Chang, D. F. Wong, C. K. Wong: Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA 1996: 80-86
5		Yao-Wen Chang, D. F. Wong, C. K. Wong: Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. 1(1): 80-101 (1996)
	1995
4		Yao-Wen Chang, D. F. Wong, C. K. Wong: FPGA global routing based on a new congestion metric. ICCD 1995: 372-
3		Yao-Wen Chang, D. F. Wong, C. K. Wong: Design and analysis of FPGA/FPIC switch modules. ICCD 1995: 394-401
	1994
2		Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong: A new global routing algorithm for FPGAs. ICCAD 1994: 356-361
	1993
1		Kai Zhu, D. F. Wong, Yao-Wen Chang: Switch module design with application to two-dimensional segmentation design. ICCAD 1993: 480-485

Coauthor Index

1	Charles J. Alpert	[156]
2	Valeriy Balabanov	[183]
3	Chen-Feng Chang	[65]
4	Hua-Yu Chang	[179] [184]
5	Ming-Tung Chang	[142]
6	Nicholas Chia-Yuan Chang	[33]
7	Yu-Dong Chang	[12] [17]
8	Yu-Tsang Chang	[22]
9	Yun-Chih Chang	[21] [23] [38]
10	Yung-Chung Chang	[128]
11	Kai-Yuan Chao	[45] [144]
12	Mango Chia-Tso Chao	[13] [27] [42]
13	Wen-Chang Chao	[87]
14	Wen-Chi Chao	[142]
15	Charlie Chung-Ping Chen (Chung-Ping Chen)	[7]
16	Duan-Ping Chen	[181]
17	Hsin-Chen Chen	[77] [82] [115] [128]
18	Hsin-Lung Chen	[30] [35] [52]
19	Huang-Yu Chen	[84] [103] [117] [127] [135] [147] [151] [154]
20	Jwu E. Chen	[57] [72] [86] [89]
21	Liang-Gee Chen	[58] [102]
22	Lumdo Chen	[84] [117]
23	Sao-Jie Chen	[40] [47] [55] [65] [70]
24	Szu-Yu Chen	[100] [119] [158] [187]
25	Tai-Chen Chen	[28] [46] [68] [85] [92] [112] [129] [152]
26	Tung-Chieh Chen	[59] [60] [64] [67] [71] [77] [82] [99] [111] [113] [115] [118] [120] [121] [124]
27	Wei-Yu Chen	[188]
28	Yen-Pin Chen	[106] [150]
29	Yu-Wei Chen	[114]
30	Chung-Chun Cheng	[166]
31	Yi-Hui Cheng	[53]
32	Mei-Fang Chiang	[84] [117]
33	Shao-Yi Chien	[58] [102]
34	Tzuo-Fan Chien	[142] [161]
35	Minsik Cho	[121] [124]
36	Pang-Yen Chou	[180] [181]
37	Sheng Chou	[178]
38	Szu-Jui Chou	[80] [98] [103] [114] [135] [154]
39	Jen-Hui Chuang	[69]
40	Yi-Lin Chuang	[99] [118] [128] [139] [156] [165] [174] [175] [177] [189]
41	Paul Falkenstern	[168]
42	Hongbing Fan	[31]
43	Jia-Wei Fang	[63] [91] [106] [110] [125] [126] [136] [145] [149] [150]
44	Shao-Yun Fang	[161] [187] [188]
45	Brian Han	[84] [117]
46	Kuan-Hsien Ho	[126] [150] [159] [167]
47	Tsung-Yi Ho	[40] [47] [55] [65] [70] [176] [177]
48	Yuan-Kai Ho	[166] [182]
49	Chin-Hsiung Hsu	[98] [110] [127] [136] [140] [147] [151] [162] [172]
50	Jer-Ming Hsu	[41]
51	Kai-Chi Hsu	[107] [122]
52	Meng-Kai Hsu	[144] [157] [178] [183]
53	Tien-Chang Hsu	[59] [77] [82] [115]
54	Jiang Hu	[76] [93] [185]
55	Few-Juh Huang	[113]
56	Fwu-Juh Huang	[111]
57	Shih-Lun Huang	[107] [122] [155] [181]
58	Tsung-Wei Huang	[176]
59	Shyh-Kang Jeng	[78]
60	Iris Hui-Ru Jiang	[13] [15] [16] [19] [33] [45] [74] [179] [184]
61	Jie-Hong Roland Jiang (Jie-Hong R. Jiang)	[98] [167]
62	Zhe-Wei Jiang	[59] [77] [79] [82] [115] [116] [131] [144]
63	Jing-Yang Jou	[15] [16] [19] [45] [48] [54] [62] [73] [74]
64	Da-Cheng Juan	[189]
65	Sangmin Kim	[165] [174]
66	Mong-Kai Ku	[58] [102]
67	Sy-Yen Kuo	[80] [114]
68	Tei-Wei Kuo	[58] [102]
69	Chun-Ying Lai	[78]
70	Chung-Len Lee	[57] [72] [86] [89]
71	D. T. Lee (Der-Tsai Lee)	[40] [55]
72	Hsu-Chieh Lee	[159] [160] [182]
73	Hsun-Cheng Lee	[41] [90]
74	Kuang-Yao Lee	[112]
75	Meng-Xiang Lee	[122]
76	Po-Wei Lee	[139] [141] [160] [175] [186]
77	Wan-Ping Lee	[81] [105] [109] [134] [138]
78	Chi-Feng Li	[100] [101] [119]
79	Chien-Mo James Li (James Chien-Mo Li, J. C.-M. Li)	[142]
80	Katherine Shu-Min Li	[57] [72] [86] [89]
81	Meng-Xiang Li	[107]
82	Guang-Wan Liao	[129] [152]
83	Kuan-Yu Liao	[142]
84	Chung-Wei Lin	[80] [100] [107] [112] [114] [119] [122] [141] [155] [186]
85	Cliff Chiung-Yu Lin	[146] [148] [164] [170] [176]
86	Hong-Ting Lin	[177]
87	I-Jye Lin	[63] [91] [97] [108]
88	Jai-Ming Lin	[10] [24] [25] [26] [27] [29] [30] [32] [35] [36] [37] [43] [56] [69]
89	Mark Po-Hung Lin	[133] [143] [171] [181]
90	Shih-Ping Lin	[34] [37] [44]
91	Shyh-Chang Lin	[64] [85] [120] [133]
92	Tzu-Hen Lin	[178]
93	Tsui-Yee Ling	[97]
94	Chen-Wei Liu	[75] [94]
95	Chih-Hung Liu	[80] [114]
96	Denny Liu	[111]
97	Dick Liu	[181]
98	Hung-Yi Liu	[80] [81] [105] [109] [114] [134]
99	T.-Y. Liu	[113]
100	Diana Marculescu	[138] [177] [189]
101	S. Muthukrishnan (S. Muthu Muthukrishnan)	[8]
102	Gi-Joon Nam	[156]
103	Sani R. Nassif	[140] [162] [172]
104	Hung-Chih Ou	[180]
105	David Z. Pan (David Zhigang Pan)	[121] [124]
106	Song-Ra Pan	[19] [20] [28] [46] [74]
107	Chih-Yang Peng	[87]
108	Jarrod A. Roy	[156]
109	Sachin S. Sapatnekar	[130] [132]
110	Prashant Saxena	[169] [173]
111	Chin-Fang Shen	[141] [186]
112	Chi-Sheng Shih	[58] [102]
113	Xin-Wei Shih	[159] [163] [166]
114	Youngsoo Shin	[165] [174]
115	Michael Shyu	[12] [14] [17]
116	Bor-Yiing Su	[66] [76] [93] [95] [131]
117	Chauchin Su	[57] [72] [86] [89]
118	Jaw-Luen Tang	[153]
119	Shashidhar Thakur	[2] [8]
120	Chia-Chun Tsai	[78]
121	Min-Hsiu Tsai	[142]
122	Ming-Chao Tsai	[112]
123	Hui-Fang Tsao	[181]
124	Chih-Mou Tseng	[142]
125	Wei-Chih Tseng	[141] [186]
126	Shang-Wei Tu	[48] [54] [62] [73]
127	Wei-Ting Tu	[80]
128	Natarajan Viswanathan	[156]
129	Jyh-Herng Wang	[63] [87] [91]
130	Sheng-Lung Wang	[103] [135]
131	Ting-Chi Wang	[112]
132	Yu Wang	[168]
133	Chak-Kuen Wong (C. K. Wong)	[3] [4] [5] [6] [39]
134	Martin D. F. Wong (D. F. Wong)	[1] [2] [3] [4] [5] [6] [7] [8] [10] [18] [24] [39] [143] [145] [171]
135	Guang-Ming Wu	[9] [11] [12] [13] [14] [17] [21] [23] [25] [26] [27] [32] [38] [39] [42] [69]
136	Meng-Chen Wu	[49]
137	Shu-Wei Wu	[23]
138	Su-Wei Wu	[51]
139	Yen-Wei Wu	[61]
140	Yu-Liang Wu (David Yu-Liang Wu)	[31]
141	Jen-Yi Wuu	[67]
142	Yuan Xie	[168]
143	Chia-Lin Yang	[50] [52] [58] [61] [83] [88] [96] [100] [101] [102] [104] [119] [123] [130] [132] [137] [176]
144	Hannah Honghua Yang (Honghua Yang)	[41] [90]
145	Shih-Yi Yuan	[114]
146	Ping-Hung Yuh	[50] [52] [61] [63] [83] [88] [96] [101] [104] [111] [113] [123] [130] [132] [137] [176]
147	Hongbo Zhang	[143] [171]
148	Kai Zhu	[1] [2] [18] [39]

Colors in the list of coauthors

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