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Soon-Jyh Chang Coauthor index pubzone.org

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DBLP keys2012
31Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang: Routability-driven placement algorithm for analog integrated circuits. ISPD 2012: 71-78
2011
30Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang: Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. DAC 2011: 528-533
29Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAn-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting: A SAR ADC BIST for simplified linearity test. SoCC 2011: 146-149
28Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, Chih-Hao Huang: Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction. IEEE Trans. VLSI Syst. 19(12): 2158-2169 (2011)
27Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJin-Fu Lin, Soon-Jyh Chang: A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages. IEICE Transactions 94-C(1): 89-101 (2011)
26Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHsin-Wen Ting, Soon-Jyh Chang, Su-Ling Huang: A Design of Linearity Built-in Self-Test for Current-Steering DAC. J. Electronic Testing 27(1): 85-94 (2011)
2010
25Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang: Performance-driven analog placement considering boundary constraint. DAC 2010: 292-297
24Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai: A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. ISSCC 2010: 386-387
23Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYing-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang: A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. IEEE Trans. VLSI Syst. 18(3): 509-513 (2010)
22Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYing-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang: An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. IEEE Trans. on Circuits and Systems 57-I(8): 1829-1837 (2010)
21Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, Chih-Hao Huang: A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique. IEEE Trans. on Circuits and Systems 57-II(3): 163-167 (2010)
20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin: A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. J. Solid-State Circuits 45(4): 731-740 (2010)
2009
19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAn-Sheng Chao, Soon-Jyh Chang: A Jitter Characterizing BIST with Pulse-Amplifying Technique. Asian Test Symposium 2009: 379-384
18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang: Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique. Asian Test Symposium 2009: 57-62
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYing-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang: A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. ISSCC 2009: 80-81
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYing-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu: A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process. IEICE Transactions 92-C(2): 258-268 (2009)
2008
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang: A Histogram-Based Testing Method for Estimating A/D Converter Performance. IEEE T. Instrumentation and Measurement 57(2): 420-427 (2008)
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu: A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR. IEEE Trans. on Circuits and Systems 55-II(11): 1089-1093 (2008)
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHsin-Hung Ou, Soon-Jyh Chang, Bin-Da Liu: Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture. IEICE Transactions 91-A(2): 461-468 (2008)
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Chien-Hung Tsai, Bin-Da Liu, Soon-Jyh Chang: A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter. IEICE Transactions 91-C(5): 809-812 (2008)
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHsin-Hung Ou, Bin-Da Liu, Soon-Jyh Chang: A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture. IEICE Transactions 91-C(9): 1480-1487 (2008)
2007
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang: Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. J. Electronic Testing 23(6): 549-558 (2007)
2006
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHeng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang: An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. APCCAS 2006: 255-258
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJin-Fu Lin, Soon-Jyh Chang: A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. ISCAS 2006
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang: Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. ISCAS 2006
2004
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang: A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. Asian Test Symposium 2004: 296-301
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang: A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. Asian Test Symposium 2004: 52-57
2003
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng: A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. Asian Test Symposium 2003: 124-129
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. 19(4): 637-651 (2003)
2002
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electronic Testing 18(6): 571-581 (2002)
1997
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Functional test pattern generation for CMOS operational amplifier. VTS 1997: 267-273

Coauthor Index

1Linkai Bu [24]
2An-Sheng Chao [19] [29]
3Jwu E. Chen [1] [2] [3]
4Lih-Yih Chiou [7]
5Yen-Chih Chiu [30]
6Chih-Hao Huang [18] [21] [24] [28]
7Chih-Haur Huang [6]
8Chun-Po Huang [25] [30]
9Chung-Ming Huang [24]
10Guan-Ying Huang [17] [20] [22] [24]
11Su-Ling Huang [26]
12Te-Chieh Kung [28]
13Chung-Len Lee [1] [2] [3]
14Kuen-Jong Lee [4] [6]
15Cheng-Wu Lin [10] [23] [25] [30] [31]
16Heng-Yao Lin [9]
17Jai-Ming Lin [25] [30] [31]
18Jin-Fu Lin [8] [18] [21] [27] [28]
19Ying-Zu Lin [14] [16] [17] [20] [22] [23] [24]
20Bin-Da Liu [5] [9] [10] [11] [12] [13] [15]
21Chun-Cheng Liu [17] [20] [21] [22] [24]
22Yen-Ting Liu [7] [14] [16] [17] [22]
23Cheng-Chung Lu [31]
24Hsin-Hung Ou [11] [13]
25Hsin-Wen Ting [5] [10] [15] [26] [28] [29]
26Chien-Hung Tsai [12]
27Chih-Chung Tsai [24]
28Hui-Hsien Tsai [9]
29Ruei-Shiuan Tzeng [4]
30Chia-Ling Wei [12]
31Lu-Yao Wu [12]
32Hsiu-Hui Yang [12]
33Jar-Ferr Yang [9]

Colors in the list of coauthors

Last update Tue May 29 01:28:40 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page