Si-En Chang

	1997
4		Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung: Instruction Cache Prefetching with Extended BTB. ICPADS 1997: 360-
	1994
3		Si-En Chang, Chia-Chang Hsu: Efficient Simulation Methods for Multi-Level Cache Memory Hierarchies. HICSS (1) 1994: 221-230
	1990
2		Si-En Chang, M. L. Manwaring, Y. Paul Chiang: Extended restricted AND-parallelism execution model. SPDP 1990: 471-474
	1989
1		Si-En Chang, Y. Paul Chiang: Restricted AND-Parallelism Execution Model with Side-Effects. NACLP 1989: 350-368

Coauthor Index

1	Shyh-An Chi	[4]
2	Y. Paul Chiang	[1] [2]
3	Jih-Ching Chiu	[4]
4	Chung-Ping Chung	[4]
5	Chia-Chang Hsu	[3]
6	M. L. Manwaring	[2]
7	R.-Ming Shiu	[4]

Colors in the list of coauthors

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