 | 2012 |
|---|
| 7 |       | Iris Hui-Ru Jiang,
Hua-Yu Chang:
ECOS: Stable Matching Based Metal-Only ECO Synthesis.
IEEE Trans. VLSI Syst. 20(3): 485-497 (2012) |
| 6 | | Iris Hui-Ru Jiang,
Hua-Yu Chang,
Chih-Long Chang:
WiT: Optimal Wiring Topology for Electromigration Avoidance.
IEEE Trans. VLSI Syst. 20(4): 581-592 (2012) |
| 2011 |
|---|
| 5 | | Hua-Yu Chang,
Iris Hui-Ru Jiang,
Yao-Wen Chang:
Simultaneous functional and timing ECO.
DAC 2011: 140-145 |
| 4 | | Hua-Yu Chang,
Iris Hui-Ru Jiang,
Yao-Wen Chang:
Timing ECO optimization via Bézier curve smoothing and fixability identification.
ICCAD 2011: 742-746 |
| 2010 |
|---|
| 3 | | Iris Hui-Ru Jiang,
Hua-Yu Chang:
Live Demo: ECOS 1.0: A metal-only ECO synthesizer.
ISCAS 2010: 2774 |
| 2 | | Iris Hui-Ru Jiang,
Hua-Yu Chang,
Chih-Long Chang:
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles.
ISPD 2010: 177-184 |
| 2009 |
|---|
| 1 | | Iris Hui-Ru Jiang,
Hua-Yu Chang,
Liang-Gi Chang,
Huang-Bi Hung:
Matching-based minimum-cost spare cell selection for design changes.
DAC 2009: 408-411 |
Data released under the ODC-BY 1.0 license — See also our legal information page