 | 2011 |
|---|
| 7 |       | Cheng-An Chien,
Yao-Chang Yang,
Hsiu-Cheng Chang,
Jia-Wei Chen,
Cheng-Yen Chang,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Hwa Cheng:
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.
ASP-DAC 2011: 73-74 |
| 2009 |
|---|
| 6 | | Hsiu-Cheng Chang,
Yao-Chang Yang,
Jia-Wei Chen,
Ching-Lung Su,
Cheng-An Chien,
Jiun-In Guo,
Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip.
ASP-DAC 2009: 125-126 |
| 5 | | Hsiu-Cheng Chang,
Jia-Wei Chen,
Yao-Chang Yang,
Cheng-An Chien,
Tzu-Chun Chang,
Jinn-Shyan Wang,
Jiun-In Guo:
A Dynamic Quality-scalable H.264 Video Encoder.
ISCAS 2009: 1932 |
| 4 | | Cheng-An Chien,
Hsiu-Cheng Chang,
Jiun-In Guo:
A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards.
ISCAS 2009: 2377-2380 |
| 3 | | Hsiu-Cheng Chang,
Jia-Wei Chen,
Bing-Tsung Wu,
Ching-Lung Su,
Jinn-Shyan Wang,
Jiun-In Guo:
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications.
IEEE Trans. Circuits Syst. Video Techn. 19(12): 1739-1754 (2009) |
| 2007 |
|---|
| 2 | | Chun-Hao Chang,
Jia-Wei Chen,
Hsiu-Cheng Chang,
Yao-Chang Yang,
Jinn-Shyan Wang,
Jiun-In Guo:
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons.
SiPS 2007: 521-526 |
| 2005 |
|---|
| 1 | | Hsiu-Cheng Chang,
Chien-Chang Lin,
Jiun-In Guo:
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding.
ISCAS (6) 2005: 6110-6113 |
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