Vinay Bhaskar Chandratre

	2011
4		Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda: 500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti". ISVLSI 2011: 72-77
3		Shiv Kumar, Vinay Bhaskar Chandratre, Sudheer K. Mohammed, C. K. Pithawa: Extraction of Aspect Ratio for Non-Manhattan CMOS Devices. VLSI Design 2011: 130-134
	2010
2		Balaji Srinivasan, Vinay Bhaskar Chandratre: An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2010: 335-338
	2008
1		Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani: 0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2008: 613-619

Coauthor Index

1	Shiv Kumar	[3]
2	Sudheer K. Mohammed	[3]
3	C. K. Pithawa	[3] [4]
4	Vangmayee Sharda	[4]
5	Balaji Srinivasan	[1] [2]
6	Menka Sukhwani	[4]
7	Menka Tewani	[1]
8	Megha Thomas	[4]

Colors in the list of coauthors

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