 | 2008 |
|---|
| 11 |       | Shrutisagar Chandrasekaran,
Abbes Amira:
High Performance FPGA Implementation of the Mersenne Twister.
DELTA 2008: 482-485 |
| 10 | | Pramod Kumar Meher,
Shrutisagar Chandrasekaran,
Abbes Amira:
FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.
IEEE Transactions on Signal Processing 56(7-1): 3009-3017 (2008) |
| 9 | | Shrutisagar Chandrasekaran,
Abbes Amira,
Minghua Shi,
Amine Bermak:
An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform.
J. Real-Time Image Processing 3(3): 183-193 (2008) |
| 8 | | Abbes Amira,
Shrutisagar Chandrasekaran,
David W. G. Montgomery,
Isa Servan Uzun:
A segmentation concept for positron emission tomography imaging using multiresolution analysis.
Neurocomputing 71(10-12): 1954-1965 (2008) |
| 2007 |
|---|
| 7 | | Shrutisagar Chandrasekaran,
Abbes Amira:
A New Behavioural Power Modelling Approach for FPGA based Custom Cores.
AHS 2007: 350-357 |
| 6 | | Shrutisagar Chandrasekaran,
Abbes Amira:
Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix Transforms.
ISCAS 2007: 3207-3210 |
| 5 | | Abbes Amira,
Shrutisagar Chandrasekaran:
Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing.
IEEE Trans. VLSI Syst. 15(3): 286-295 (2007) |
| 2006 |
|---|
| 4 | | Shrutisagar Chandrasekaran,
Abbes Amira:
Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling.
FPL 2006: 1-2 |
| 3 | | Shrutisagar Chandrasekaran,
Abbes Amira:
FPGA Implementation and Power Modelling of the Fast Walsh Transform.
FPL 2006: 1-4 |
| 2005 |
|---|
| 2 |  | Shrutisagar Chandrasekaran,
Abbes Amira:
High Speed / Low Power Architectures for the Finite Radon Transform.
FPL 2005: 450-455 |
| 1 | | Shrutisagar Chandrasekaran,
Abbes Amira:
An area efficient low power inner product computation for discrete orthogonal transforms.
ICIP (3) 2005: 1024-1027 |
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