Nitin Chandrachoodan

	2012
14		Dhiraj Reddy Nallapa Yoge, Nitin Chandrachoodan: GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications. VLSI Design 2012: 149-154
13		Manish Kumar Jaiswal, Nitin Chandrachoodan: FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture. IEEE Trans. Computers 61(1): 60-72 (2012)
	2011
12		Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti: Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. ISVLSI 2011: 319-320
11		Nitin Chandrachoodan, Shankar Balachandran: 24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011. J. Low Power Electronics 7(4): 459 (2011)
	2009
10		Manish Kumar Jaiswal, Nitin Chandrachoodan: Efficient Implementation of Floating-Point Reciprocator on FPGA. VLSI Design 2009: 267-271
	2008
9		Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan: Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. VLSI Design 2008: 169-174
	2007
8		Karthick Parashar, Nitin Chandrachoodan: A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation. FPL 2007: 792-795
7		Kannan Gaddam, Nitin Chandrachoodan, S. Srinivasan: Rapid Abstract Control Model for Signal Processing Implementation. SiPS 2007: 418-423
	2004
6		Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu: The hierarchical timing pair model for multirate DSP applications. IEEE Transactions on Signal Processing 52(5): 1209-1217 (2004)
	2003
5		Arun Raghupathy, Nitin Chandrachoodan, K. J. Ray Liu: Algorithm and VLSI architecture for high performance adaptive video scaling. IEEE Transactions on Multimedia 5(4): 489-502 (2003)
	2002
4		Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu: High-Level Synthesis of DSP Applications Using Adaptive Negative Cycle Detection. EURASIP J. Adv. Sig. Proc. 2002(9): 893-907 (2002)
	2001
3		Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu: Adaptive negative cycle detection in dynamic graphs. ISCAS (5) 2001: 163-166
2		Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu: The hierarchical timing pair model. ISCAS (5) 2001: 367-370
	1999
1		Arun Raghupathy, Pohsiang Hsu, K. J. Ray Liu, Nitin Chandrachoodan: VLSI architecture and design for high performance adaptive video scaling. ISCAS (4) 1999: 406-409

Coauthor Index

1	Shankar Balachandran	[11]
2	Shuvra S. Bhattacharyya	[2] [3] [4] [6]
3	Kannan Gaddam	[7]
4	Pohsiang Hsu	[1]
5	Manish Kumar Jaiswal	[10] [13]
6	V. Kamakoti	[12]
7	Aman Kokrady	[9]
8	K. J. Ray Liu	[1] [2] [3] [4] [5] [6]
9	Karthick Parashar	[8]
10	Seetal Potluri	[12]
11	Arun Raghupathy	[1] [5]
12	C. P. Ravikumar	[9]
13	S. Srinivasan	[7]
14	Dhiraj Reddy Nallapa Yoge	[14]

Colors in the list of coauthors

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