Rajeevan Chandel

	2012
5		Rohit Dhiman, Rajeevan Chandel: Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications. J. Low Power Electronics 8(1): 39-46 (2012)
	2010
4		Kiran K. Chaddha, Rajeevan Chandel: Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique. J. Low Power Electronics 6(4): 482-490 (2010)
3		Ashutosh Nandi, Rajeevan Chandel: Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications. J. Low Power Electronics 6(4): 513-520 (2010)
	2007
2		Rajeevan Chandel, Sankar Sarkar, Ashwani Chandel: Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects. J. Low Power Electronics 3(3): 337-344 (2007)
1		Rajeevan Chandel, Sankar Sarkar, Rajendra Prasad Agarwal: An analysis of interconnect delay minimization by low-voltage repeater insertion. Microelectronics Journal 38(4-5): 649-655 (2007)

Coauthor Index

1	Rajendra Prasad Agarwal	[1]
2	Kiran K. Chaddha	[4]
3	Ashwani Chandel	[2]
4	Rohit Dhiman	[5]
5	Ashutosh Nandi	[3]
6	Sankar Sarkar	[1] [2]

Colors in the list of coauthors

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