Pak K. Chan

	2003
25		Pak K. Chan, Martine D. F. Schlag: Parallel placement for field-programmable gate arrays. FPGA 2003: 43-50
	2000
24		Pak K. Chan, Martine D. F. Schlag: New parallelization and convergence results for NC: a negotiation-based FPGA router. FPGA 2000: 165-174
23		Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie: Distributed-memory parallel routing for field-programmable gatearrays. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 850-862 (2000)
	1999
22		Pak K. Chan, Mark J. Boyd, Sezer Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu: Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. FCCM 1999: 308-309
21		Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan: Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1389-1399 (1999)
	1997
20		Pak K. Chan, Martine D. F. Schlag: Acceleration of an FPGA router. FCCM 1997: 175-181
19		Jason Y. Zien, Pak K. Chan, Martine D. F. Schlag: Hybrid spectral/iterative partitioning. ICCAD 1997: 436-440
	1996
18		Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan: Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. ICCAD 1996: 201-204
17		Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien: Spectral-based multiway FPGA partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 554-560 (1996)
	1995
16		Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien: Spectral-Based Multi-Way FPGA Partitioning. FPGA 1995: 133-139
	1994
15		Martine D. F. Schlag, Jackson Kong, Pak K. Chan: Routability-driven technology mapping for lookup table-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 13-26 (1994)
14		Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien: Spectral K-way ratio-cut partitioning and clustering. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1088-1096 (1994)
	1993
13		Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien: On Routability Prediction for Field-Programmable Gate Arrays. DAC 1993: 326-330
12		Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien: Spectral K-Way Ratio-Cut Partitioning and Clustering. DAC 1993: 749-754
11		Martine D. F. Schlag, Pak K. Chan, Jackson Kong: Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 713-722 (1993)
	1992
10		Martine D. F. Schlag, Jackson Kong, Pak K. Chan: Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. ICCD 1992: 86-90
9		Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija: Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. IEEE Trans. Computers 41(8): 920-930 (1992)
	1991
8		Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija: Delay optimization of carry-skip adders and block carry-lookahead adders. IEEE Symposium on Computer Arithmetic 1991: 154-164
7		Pak K. Chan: Comments on `Asymptotic waveform evaluation for timing analysis'. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1078-1079 (1991)
	1990
6		Pak K. Chan: Algorithms for Library-Specific Sizing of Combinational Logic. DAC 1990: 353-356
5		Pak K. Chan, Martine D. F. Schlag: Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. IEEE Trans. Computers 39(8): 983-992 (1990)
4		Pak K. Chan, Kevin Karplus: Computing signal delay in general RC networks by tree/link partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 898-902 (1990)
	1989
3		Pak K. Chan, Kevin Karplus: Computing Signal Delay in General RC Networks by Tree/Link Partitioning. DAC 1989: 485-490
2		Pak K. Chan, Martine D. F. Schlag: Analysis and design of CMOS Manchester adders with variable carry-skip. IEEE Symposium on Computer Arithmetic 1989: 86-95
1		Pak K. Chan, Martine D. F. Schlag: Bounds on signal delay in RC mesh networks. IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 581-589 (1989)

Coauthor Index

1	Mark J. Boyd	[22]
2	Carl Ebeling	[23]
3	Sezer Gören	[22]
4	Kevin Karplus	[3] [4]
5	K. Klenk	[22]
6	V. Kodavati	[22]
7	Jackson Kong	[10] [11] [15]
8	R. Kundu	[22]
9	M. Margolese	[22]
10	Larry McMurchie	[23]
11	Vojin G. Oklobdzija	[8] [9]
12	Martine D. F. Schlag	[1] [2] [5] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [23] [24] [25]
13	J. Sun	[22]
14	K. Suzuki	[22]
15	Clark D. Thomborson (Clark D. Thompson)	[8] [9]
16	E. Thorne	[22]
17	X. Wang	[22]
18	J. Xu	[22]
19	M. Zhu	[22]
20	Jason Y. Zien	[12] [13] [14] [16] [17] [18] [19] [21]

Colors in the list of coauthors

Last update Tue May 29 01:28:40 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page