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Víctor H. Champac Vilela
List of publications from the DBLP Bibliography Server - FAQ
| 2011 | ||
|---|---|---|
| 35 | Jesus Moreno, Víctor H. Champac, Michel Renovell: A new methodology for realistic open defect detection probability evaluation under process variations. VTS 2011: 184-189 | |
| 34 | C. V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. VTS 2011: 203-208 | |
| 33 | Jose Luis Garcia-Gervacio, Víctor H. Champac: Computing the Detection Probability for Small Delay Defects of Nanometer ICs. J. Electronic Testing 27(6): 741-752 (2011) | |
| 32 | Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Leticia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian: 12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electronics 7(4): 529-530 (2011) | |
| 2010 | ||
| 31 | Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira: Programmable aging sensor for automotive safety-critical applications. DATE 2010: 618-621 | |
| 30 | Jose Luis Garcia-Gervacio, Víctor H. Champac: Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. European Test Symposium 2010: 126-131 | |
| 29 | Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira: Predictive error detection by on-line aging monitoring. IOLTS 2010: 9-14 | |
| 28 | Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira: Low-sensitivity to process variations aging sensor for automotive safety-critical applications. VTS 2010: 238-243 | |
| 27 | Víctor H. Champac, Victor Avendaño, Joan Figueras: Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. IEEE Trans. VLSI Syst. 18(2): 256-269 (2010) | |
| 2009 | ||
| 26 | Jose Luis Garcia-Gervacio, Víctor H. Champac: Detectability analysis of small delays due to resistive opens considering process variations. IOLTS 2009: 195-197 | |
| 25 | Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira: Built-in aging monitoring for safety-critical applications. IOLTS 2009: 9-14 | |
| 24 | Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura: Stuck-Open Fault Leakage and Testing in Nanometer Technologies. VTS 2009: 315-320 | |
| 2008 | ||
| 23 | Daniel Iparraguirre-Cardenas, Jose Luis Garcia-Gervacio, Víctor H. Champac: A design methodology for logic paths tolerant to local intra-die variations. ISCAS 2008: 596-599 | |
| 22 | Nestor Hernandez, Víctor H. Champac: Testing Skew and Logic Faults in SoC Interconnects. ISVLSI 2008: 151-156 | |
| 21 | Roberto Gómez, Alejandro Girón, Víctor H. Champac: A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. J. Electronic Testing 24(6): 529-538 (2008) | |
| 2007 | ||
| 20 | Antonio Zenteno Ramirez, Guillermo Espinosa, Víctor H. Champac: Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. IEEE Trans. VLSI Syst. 15(5): 572-577 (2007) | |
| 2005 | ||
| 19 | Roberto Gómez, Alejandro Girón, Víctor H. Champac: Test of Interconnection Opens Considering Coupling Signals. DFT 2005: 247-258 | |
| 2004 | ||
| 18 | Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs: Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium 2004: 460-463 | |
| 17 | Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac Vilela: An improved technique to increase noise-tolerance in dynamic digital circuits. ISCAS (2) 2004: 489-492 | |
| 16 | Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac Vilela: The noise immunity of dynamic digital circuits with technology scaling. ISCAS (2) 2004: 493-496 | |
| 15 | Fabian Vargas, Víctor H. Champac: Guest Editorial. J. Electronic Testing 20(4): 331-332 (2004) | |
| 2003 | ||
| 14 | Víctor H. Champac, Ingrid Jansch-Pôrto: Guest Editorial. J. Electronic Testing 19(1): 11 (2003) | |
| 2002 | ||
| 13 | Fernando Mendoza-Hernandez, M. Linares, Víctor H. Champac, A. Diaz-Sanchez: A new technique for noise-tolerant pipelined dynamic digital circuits. ISCAS (4) 2002: 185-188 | |
| 2001 | ||
| 12 | Antonio Zenteno, Víctor H. Champac: Resistive Opens in a Class of CMOS Latches: Analysis and DFT. VTS 2001: 138-144 | |
| 11 | Marcelo Lubaszewski, Víctor H. Champac: Guest Editorial. J. Electronic Testing 17(2): 83-84 (2001) | |
| 10 | Antonio Zenteno, Víctor H. Champac, Joan Figueras: Detectability Conditions of Full Opens in the Interconnections. J. Electronic Testing 17(2): 85-95 (2001) | |
| 2000 | ||
| 9 | Víctor H. Champac, Antonio Zenteno: Detectability Conditions for Interconnection Open Defect. VTS 2000: 305-312 | |
| 8 | Gordana Jovanovic-Dolecek, Víctor H. Champac: CGTDEMO - educational software for the central limit theorem. SIGCSE Bulletin 32(2): 46-48 (2000) | |
| 1999 | ||
| 7 | Víctor H. Champac, José Castillejos, Joan Figueras: IDDQ Testing of Opens in CMOS SRAMs. J. Electronic Testing 15(1-2): 53-62 (1999) | |
| 1998 | ||
| 6 | Víctor H. Champac, José Castillejos, Joan Figueras: IDDQ Testing of Opens in CMOS SRAMs. VTS 1998: 106-111 | |
| 1995 | ||
| 5 | Víctor H. Champac, Joan Figueras: Testability of floating gate defects in sequential circuits. VTS 1995: 202-207 | |
| 1994 | ||
| 4 | Víctor H. Champac, Antonio Rubio, Joan Figueras: Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 359-369 (1994) | |
| 1993 | ||
| 3 | Víctor H. Champac, Antonio Rubio, Joan Figueras: Analysis of the Floating Gate Defect in CMOS. DFT 1993: 101-108 | |
| 1992 | ||
| 2 | J. A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio: Quiescent current analysis and experimentation of defective CMOS circuits. J. Electronic Testing 3(4): 337-348 (1992) | |
| 1991 | ||
| 1 | Rosa Rodríguez-Montañés, J. A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio: Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. ITC 1991: 510-519 | |
Colors in the list of coauthors
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