Sreejit Chakravarty

	2012
93		Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty: Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits. J. Low Power Electronics 8(2): 235-247 (2012)
92		Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen: Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. J. Low Power Electronics 8(2): 248-258 (2012)
	2011
91		Sreejit Chakravarty: A Process Monitor Based Speed Binning and Die Matching Algorithm. Asian Test Symposium 2011: 311-316
90		Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas: Optimal manufacturing flow to determine minumum operating voltage. ITC 2011: 1-10
89		Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty: Power-safe test application using an effective gating approach considering current limits. VTS 2011: 160-165
	2010
88		Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty: Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test. Asian Test Symposium 2010: 301-306
87		Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh: Modified Scan Flip-Flop for Low Power Testing. Asian Test Symposium 2010: 367-370
86		Fan Yang, Sreejit Chakravarty: Testing of latch based embedded arrays using scan tests. ITC 2010: 104-113
85		Sreejit Chakravarty: Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors. VTS 2010: 350
84		Sean H. Wu, Sreejit Chakravarty, Li-C. Wang: Impact of multiple input switching on delay test under process variation. VTS 2010: 87-92
	2009
83		Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detectability of internal bridging faults in scan chains. ASP-DAC 2009: 678-683
82		Nicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum: Path selection for monitoring unexpected systematic timing effects. ASP-DAC 2009: 781-786
81		Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Improving the Detectability of Resistive Open Faults in Scan Cells. DFT 2009: 383-391
80		Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty: Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. VLSI Syst. 17(5): 697-708 (2009)
	2008
79		Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT 2008: 394-402
78		Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: An Enhanced Logic BIST Architecture for Online Testing. IOLTS 2008: 10-15
77		Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detection of Internal Stuck-open Faults in Scan Chains. ITC 2008: 1-10
76		I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty: An Industrial Case Study of Sticky Path-Delay Faults. VTS 2008: 395-402
75		Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: On the Detectability of Scan Chain Internal Faults — An Industrial Case Study. VTS 2008: 79-84
74		Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J. Electronic Testing 24(1-3): 259-269 (2008)
	2006
73		Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: An Approach to Minimizing Functional Constraints. DFT 2006: 215-226
72		Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty: A Study of Implication Based Pseudo Functional Testing. ITC 2006: 1-10
71		Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi: Exact At-speed Delay Fault Grading in Sequential Circuits. ITC 2006: 1-10
70		Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty: Path Delay Fault Simulation on Large Industrial Designs. VTS 2006: 16-23
69		Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty: Silicon Evaluation of Logic Proximity Bridge Patterns. VTS 2006: 78-85
68		Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi: Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2954-2964 (2006)
	2005
67		Sreejit Chakravarty: Improving Logic Test Quality of Microprocessors. Asian Test Symposium 2005
66		Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty: Untestable Multi-Cycle Path Delay Faults in Industrial Designs. Asian Test Symposium 2005: 194-201
65		Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi: Implicit and Exact Path Delay Fault Grading in Sequential Circuits. DATE 2005: 990-995
64		Eric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty: Logic proximity bridges. ITC 2005: 10
63		Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee: Transition Tests for High Performance Microprocessors. VTS 2005: 29-34
62		Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee: Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. VTS 2005: 337-342
61		Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Efficient techniques for transition testing. ACM Trans. Design Autom. Electr. Syst. 10(2): 258-278 (2005)
	2004
60		Manan Syal, Michael S. Hsiao, Sreejit Chakravarty: Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. ITC 2004: 1034-1043
59		Sreejit Chakravarty, Eric W. Savage, Eric N. Tran: Defect Coverage Analysis of Partitioned Testing. ITC 2004: 907-915
58		Sujit T. Zachariah, Sreejit Chakravarty: Extraction of two-node bridges from large industrial circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 433-439 (2004)
	2003
57		Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty: Efficient Implication - Based Untestable Bridge Fault Identifier. VTS 2003: 393-402
56		Sujit T. Zachariah, Sreejit Chakravarty: Algorithm to extract two-node bridges. IEEE Trans. VLSI Syst. 11(4): 741-744 (2003)
55		Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. J. Electronic Testing 19(4): 437-445 (2003)
	2002
54		Sreejit Chakravarty: Supplemental Test Methods (Tutorial Abstract). ISQED 2002: 7
53		Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah: Experimental Evaluation of Scan Tests for Bridges. ITC 2002: 509-518
52		Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Techniques to Reduce Data Volume and Application Time for Transition Test. ITC 2002: 983-992
51		Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah: Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. VTS 2002: 367-372
50		Sreejit Chakravarty, Ankur Jain: Fault Models for Speed Failures Caused by Bridges and Opens. VTS 2002: 373-378
	2001
49		Sujit T. Zachariah, Sreejit Chakravarty: A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. VLSI Design 2001: 333-338
48		Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty: Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001)
47		Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty: Automatic generation and compaction of March tests for memory arrays. IEEE Trans. VLSI Syst. 9(6): 845-857 (2001)
	2000
46		Sujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth: A novel algorithm to extract two-node bridges. DAC 2000: 790-793
45		Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota: An analysis of the delay defect detection capability of the ECR test method. ITC 2000: 1060-1069
44		Sujit T. Zachariah, Sreejit Chakravarty: A scalable and efficient methodology to extract two node bridges from large industrial circuits. ITC 2000: 750-759
43		Sreejit Chakravarty, Sujit T. Zachariah: STBM: a fast algorithm to simulate IDDQ tests forleakage faults. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 568-576 (2000)
	1999
42		Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu: On Detecting Bridges Causing Timing Failures. ICCD 1999: 400-406
41		Sujit T. Zachariah, Sreejit Chakravarty: A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. VLSI Design 1999: 91-94
40		Sreejit Chakravarty, Vinodh Gopal: Techniques to Encode and Compress Fault Dictionaries. VTS 1999: 195-200
	1998
39		Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty: A new framework for generating optimal March tests for memory arrays. ITC 1998: 73-82
38		Vinay Dabholkar, Sreejit Chakravarty: Computing Stress Tests for Gate Oxide Shorts. VLSI Design 1998: 378-391
37		Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy: Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1325-1333 (1998)
36		Yiming Gong, Sreejit Chakravarty: Locating bridging faults using dynamically computed stuck-at fault dictionaries. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 876-887 (1998)
	1997
35		Vinay Dabholkar, Sreejit Chakravarty: Computing stress tests for interconnect defects. Asian Test Symposium 1997: 143-148
34		Sreejit Chakravarty: On the capability of delay tests to detect bridges and opens. Asian Test Symposium 1997: 314-319
33		Yiming Gong, Sreejit Chakravarty: Using fault sampling to compute I/sub DDQ/ diagnostic test set. VTS 1997: 74-79
32		Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel: Algorithms to compute bridging fault coverage of IDDQ test sets. ACM Trans. Design Autom. Electr. Syst. 2(3): 281-305 (1997)
	1996
31		Paul J. Thadikaran, Sreejit Chakravarty: Fast Algorithms for Computer IDDQ Tests for Combination Circuits. VLSI Design 1996: 103-106
30		Sreejit Chakravarty: A sampling technique for diagnostic fault simulation. VTS 1996: 192-197
29		Sreejit Chakravarty, Paul J. Thadikaran: Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. IEEE Trans. Computers 45(10): 1131-1140 (1996)
28		Sreejit Chakravarty: A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. IEEE Trans. Computers 45(8): 985-991 (1996)
27		Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman: Diagnostic simulation of stuck-at faults in combinational circuits. J. Electronic Testing 8(1): 87-97 (1996)
26		Sreejit Chakravarty, Paul J. Thadikaran: Algorithms to select IDDQ measurement points to detect bridging faults. J. Electronic Testing 8(3): 275-285 (1996)
	1995
25		Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel: Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC 1995: 133-138
24		Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel: Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. FTCS 1995: 340-349
23		Yiming Gong, Sreejit Chakravarty: On adaptive diagnostic test generation. ICCAD 1995: 181-184
22		Sreejit Chakravarty, Yiming Gong: Voting model based diagnosis of bridging faults in combinational circuits. VLSI Design 1995: 338-342
21		Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel: Cyclic stress tests for full scan circuits. VTS 1995: 89-94
20		Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois: Conference Reports. IEEE Design & Test of Computers 12(4): 95-97 (1995)
	1994
19		Sreejit Chakravarty, Paul J. Thadikaran: A Study of IDDQ Subset Selection Algorithms for Bridging Faults. ITC 1994: 403-412
18		Sreejit Chakravarty, Sivaprakasam Suresh: IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. VLSI Design 1994: 179-182
	1993
17		Sreejit Chakravarty, Yiming Gong: An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. DAC 1993: 520-524
16		Sreejit Chakravarty: A Characterization of Binary Decision Diagrams. IEEE Trans. Computers 42(2): 129-137 (1993)
	1992
15		Sreejit Chakravarty, Minsheng Liu: Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. DAC 1992: 353-356
14		Sreejit Chakravarty, Minsheng Liu: Algorithms for IDDQ measurement based diagnosis of bridging faults. J. Electronic Testing 3(4): 377-385 (1992)
13		Sreejit Chakravarty, Ajay Shekhawat: Parallel and serial heuristics for the minimum set cover problem. The Journal of Supercomputing 5(4): 331-345 (1992)
	1991
12		Sreejit Chakravarty, Xin He, S. S. Ravi: Minimum area layout of series-parallel transistor networks is NP-hard. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 943-949 (1991)
11		Sreejit Chakravarty: A characterization of robust test-pairs for stuck-open faults. J. Electronic Testing 1(4): 275-286 (1991)
	1990
10		Sreejit Chakravarty: On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). DAC 1990: 736-739
9		Ajay Shekhawat, Sreejit Chakravarty: Heuristics for the MSC Problem for Serial and Shared-Memory Computers. ICPP (3) 1990: 64-67
8		Sreejit Chakravarty, Harry B. Hunt III: On Computing Signal Probability and Detection Probability of Stuck-at Faults. IEEE Trans. Computers 39(11): 1369-1377 (1990)
7		Sreejit Chakravarty, S. S. Ravi: Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 329-331 (1990)
	1989
6		Sreejit Chakravarty: A Testable Realization of CMOS Combinational Circuits. ITC 1989: 509-518
5		Sreejit Chakravarty, Harry B. Hunt III: A Note on Detecting Sneak Paths in Transistor Networks. IEEE Trans. Computers 38(6): 861-864 (1989)
4		Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz: The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits. IEEE Trans. Computers 38(6): 865-869 (1989)
3		Sreejit Chakravarty: On the complexity of computing tests for CMOS gates. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 973-980 (1989)
	1988
2		Sreejit Chakravarty, Shambhu J. Upadhyaya: A Unified Approach to Designing Fault-Tolerant Processor Ensembles. ICPP (1) 1988: 339-342
	1986
1		Sreejit Chakravarty, Harry B. Hunt III: On the Computation of Detection Probability for Multiple Faults. ITC 1986: 252-262

Coauthor Index

1	Pouria Bastani	[82]
2	Nicholas Callegari	[82]
3	Michael J. Carruthers	[51]
4	Kameshwar Chandrasekar	[72]
5	Yi-Shing Chang	[62] [63] [72] [73] [74] [76]
6	Bernard Courtois	[20]
7	Vinay Dabholkar	[21] [35] [37] [38]
8	Binh Dang	[90]
9	Narendra Devta-Prasanna	[75] [77] [78] [79] [81] [83]
10	Kiran B. Doreswamy	[57]
11	Darcy Escovedo	[90]
12	W. Kent Fuchs	[25] [48]
13	Vijay Gangaram	[80]
14	Patrick Girard	[92]
15	Yiming Gong	[17] [22] [23] [27] [33] [36]
16	Vinodh Gopal	[40]
17	Sandeep K. Gupta	[76]
18	A. J. Haas	[90]
19	Ismed Hartanto	[25] [48]
20	Xin He	[12]
21	Hiep Hoang	[62] [63]
22	Michael S. Hsiao	[52] [55] [57] [60] [61] [66] [72]
23	I-De Huang	[76]
24	Harry B. Hunt III	[1] [4] [5] [8]
25	Ankur Jain	[50] [53]
26	Abhijit Jas	[73] [74]
27	Rathish Jayabharathi	[65] [68] [71]
28	Sridhar Jayaraman	[62]
29	Niraj K. Jha	[80]
30	Bozena Kaminska	[20]
31	Vishwashanth Kasulasrinivas	[69]
32	Seonki Kim	[45]
33	Kambiz Komeyli	[51]
34	Vamsee Krishna	[64]
35	Mahilchi Milir Vaseekar Kumar	[65] [68] [71]
36	Sandip Kundu	[42]
37	Loganathan Lingappan	[80]
38	Minsheng Liu	[14] [15]
39	Xiao Liu	[52] [55] [61]
40	Junxia Ma	[88]
41	Sreenivas Mandava	[42]
42	Amit Mishra	[87]
43	J. Najm	[21]
44	Suriyaprakash Natarajan	[66] [70]
45	Janak H. Patel	[21] [24] [25] [32] [48]
46	Srinivas Patil	[70]
47	Gil Philips	[20]
48	Silvio Picano	[62]
49	Irith Pomeranz	[37] [75] [77] [78] [79] [81] [83]
50	Cheryl Prunty	[62]
51	Nandakumar Radhakrishnan	[53]
52	S. S. Ravi	[4] [7] [12]
53	Sudhakar M. Reddy	[37] [75] [77] [78] [79] [81] [83]
54	Daniel J. Rosenkrantz	[4]
55	Carl D. Roth	[46]
56	Elizabeth M. Rudnick	[25] [48]
57	Hassan Salmani	[92]
58	Satdev	[87]
59	Eric W. Savage	[51] [53] [59] [62]
60	Rehan Sheikh	[62]
61	Ajay Shekhawat	[9] [13]
62	Adit D. Singh	[87]
63	Virendra Singh	[87]
64	Nidhi Sinha	[87]
65	Ramalingam Sridhar	[20]
66	Bret T. Stastny	[51]
67	Sivaprakasam Suresh	[18]
68	Manan Syal	[57] [60] [66] [72]
69	Mohammad Tehranipoor	[88] [89] [92] [93]
70	Alexander Tetelbaum	[82]
71	Paul J. Thadikaran	[19] [24] [26] [29] [31] [32] [52] [55] [61]
72	Nick Thorpe	[63]
73	Spyros Tragoudas	[65] [68] [71]
74	Eric N. Tran	[59] [62] [64] [69]
75	Shambhu J. Upadhyaya	[2] [20] [39] [47]
76	Srikanth Venkataraman	[25] [27] [48]
77	Vishnu C. Vimjam	[72]
78	Bapiraju Vinnakota	[45]
79	Li-C. Wang	[82] [84]
80	Khen Wee	[62] [63]
81	Xiaoqing Wen	[92]
82	Sean H. Wu	[84]
83	Fan Yang	[75] [77] [78] [79] [81] [83] [86]
84	Sujit T. Zachariah	[41] [43] [44] [46] [49] [51] [53] [56] [58] [64]
85	Kamran Zarrineh	[39] [47]
86	Wei Zhao	[88] [89] [92] [93]
87	Yervant Zorian	[20]

Colors in the list of coauthors

Last update Tue May 29 01:28:40 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page