 | 2010 |
| 23 |  | Michele Portolan,
Suresh Goyal,
Bradford G. Van Treuren,
Chen-Huan Chiang,
Tapan J. Chakraborty,
Thomas B. Cook:
A Common Language Framework for Next-Generation Embedded Testing.
IEEE Design & Test of Computers 27(5): 36-49 (2010) |
| 2008 |
| 22 |  | Michele Portolan,
Suresh Goyal,
Bradford G. Van Treuren,
Chen-Huan Chiang,
Tapan J. Chakraborty,
Thomas B. Cook:
A New Language Approach for IJTAG.
ITC 2008: 1-10 |
| 21 |  | Aditya Jagirdar,
Roystein Oliveira,
Tapan J. Chakraborty:
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits.
VLSI Design 2008: 39-44 |
| 2007 |
| 20 |  | Roystein Oliveira,
Aditya Jagirdar,
Tapan J. Chakraborty:
A TMR Scheme for SEU Mitigation in Scan Flip-Flops.
ISQED 2007: 905-910 |
| 19 |  | Tapan J. Chakraborty,
Chen-Huan Chiang,
Bradford G. Van Treuren:
A practical approach to comprehensive system test & debug using boundary scan based test architecture.
ITC 2007: 1-10 |
| 18 |  | Brendan Mullane,
Chen-Huan Chiang,
Michael Higgins,
Ciaran MacNamee,
Tapan J. Chakraborty,
Thomas B. Cook:
FPGA Prototyping of a Scan Based System-On-Chip Design.
ReCoSoC 2007: 121-126 |
| 2005 |
| 17 |  | Tapan J. Chakraborty:
Efficient Test Architecture based on Boundary Scan for Comprehensive System Test.
Asian Test Symposium 2005: 464-465 |
| 2002 |
| 16 |  | Tapan J. Chakraborty,
Chen-Huan Chiang:
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.
ITC 2002: 923-929 |
| 2000 |
| 15 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
Path delay fault simulation of sequential circuits.
IEEE Trans. VLSI Syst. 8(2): 223-228 (2000) |
| 14 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
Improving path delay testability of sequential circuits.
IEEE Trans. VLSI Syst. 8(6): 736-741 (2000) |
| 1998 |
| 13 |  | Nilanjan Mukherjee,
Tapan J. Chakraborty,
Sudipta Bhawmik:
A BIST scheme for the detection of path-delay faults.
ITC 1998: 422-431 |
| 1997 |
| 12 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal:
Effective Path Selection for Delay Fault Testing of Sequential Circuits.
ITC 1997: 998-1003 |
| 11 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
On variable clock methods for path delay testing of sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1237-1249 (1997) |
| 1996 |
| 10 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal:
Design for high-speed testability of stuck-at faults.
VLSI Design 1996: 53-56 |
| 1995 |
| 9 |  | Vishwani D. Agrawal,
Tapan J. Chakraborty:
High-Performance Circuit Testing with Slow-Speed Testers.
ITC 1995: 302-310 |
| 8 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal:
Robust testing for stuck-at faults.
VLSI Design 1995: 42-46 |
| 7 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal:
Simulation of at-speed tests for stuck-at faults.
VTS 1995: 216-220 |
| 1993 |
| 6 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
Design for Testability for Path Delay faults in Sequential Circuits.
DAC 1993: 453-457 |
| 1992 |
| 5 |  | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
Delay Fault Models and Test Generation for Random Logic Sequential Circuits.
DAC 1992: 165-172 |
| 1991 |
| 4 |  | Tapan J. Chakraborty,
Sudipta Bhawmik,
Robert Bencivenga,
Chih-Jen Lin:
Enhanced Controllability for IDDQ Test Sets Using Partial Scan.
DAC 1991: 278-281 |
| 3 |  | Sumit Ghosh,
Tapan J. Chakraborty:
On behavior fault modeling for digital designs.
J. Electronic Testing 2(2): 135-151 (1991) |
| 1989 |
| 2 |  | Wu-Tung Cheng,
Tapan J. Chakraborty:
Gentest: An Automatic Test-Generation System for Sequential Circuits.
IEEE Computer 22(4): 43-49 (1989) |
| 1988 |
| 1 |  | Tapan J. Chakraborty,
Sumit Ghosh:
On Behavior Fault Modeling for Combinational Digital Designs.
ITC 1988: 593-600 |