 | 2011 |
| 21 |  | Shashikanth Bobba,
Ashutosh Chakraborty,
Olivier Thomas,
Perrine Batude,
Thomas Ernst,
Olivier Faynot,
David Z. Pan,
Giovanni De Micheli:
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.
ASP-DAC 2011: 336-343 |
| 20 |  | Ashutosh Chakraborty,
David Z. Pan:
Controlling NBTI degradation during static burn-in testing.
ASP-DAC 2011: 597-602 |
| 2010 |
| 19 |  | Shashikanth Bobba,
Ashutosh Chakraborty,
Olivier Thomas,
Perrine Batude,
Vasilis F. Pavlidis,
Giovanni De Micheli:
Performance analysis of 3-D monolithic integrated circuits.
3DIC 2010: 1-4 |
| 18 |  | Krit Athikulwongse,
Ashutosh Chakraborty,
Jae-Seok Yang,
David Z. Pan,
Sung Kyu Lim:
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.
ICCAD 2010: 669-674 |
| 17 |  | Ashutosh Chakraborty,
David Z. Pan:
PASAP: power aware structured ASIC placement.
ISLPED 2010: 395-400 |
| 16 |  | Ashutosh Chakraborty,
David Z. Pan:
Skew management of NBTI impacted gated clock trees.
ISPD 2010: 127-133 |
| 15 |  | Ashutosh Chakraborty,
Sean X. Shi,
David Z. Pan:
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1533-1545 (2010) |
| 14 |  | Ashutosh Chakraborty,
Karthik Duraisami,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.
IEEE Trans. on Circuits and Systems 57-I(10): 2741-2752 (2010) |
| 2009 |
| 13 |  | Ashutosh Chakraborty,
Anurag Kumar,
David Z. Pan:
RegPlace: a high quality open-source placement framework for structured ASICs.
DAC 2009: 442-447 |
| 12 |  | Ashutosh Chakraborty,
Gokul Ganesan,
Anand Rajaram,
David Z. Pan:
Analysis and optimization of NBTI induced clock skew in gated clock trees.
DATE 2009: 296-299 |
| 11 |  | Ashutosh Chakraborty,
David Z. Pan:
On stress aware active area sizing, gate sizing, and repeater insertion.
ISPD 2009: 35-42 |
| 2008 |
| 10 |  | Tung-Chieh Chen,
Ashutosh Chakraborty,
David Z. Pan:
An integrated nonlinear placement framework with congestion and porosity aware buffer planning.
DAC 2008: 702-707 |
| 9 |  | Ashutosh Chakraborty,
Sean X. Shi,
David Z. Pan:
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.
DATE 2008: 849-855 |
| 8 |  | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.
IEEE Trans. VLSI Syst. 16(6): 639-649 (2008) |
| 7 |  | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
Integration 41(1): 2-8 (2008) |
| 2006 |
| 6 |  | Ashutosh Chakraborty,
Prassanna Sithambaram,
Karthik Duraisami,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Thermal resilient bounded-skew clock tree optimization methodology.
DATE 2006: 832-837 |
| 5 |  | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
ISCAS 2006 |
| 4 |  | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic thermal clock skew compensation using tunable delay buffers.
ISLPED 2006: 162-167 |
| 3 |  | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
PATMOS 2006: 214-224 |
| 2005 |
| 2 |  | Ashutosh Chakraborty,
Enrico Macii,
Massimo Poncino:
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.
PATMOS 2005: 297-307 |
| 2003 |
| 1 |  | Pradeep Varma,
Ashutosh Chakraborty:
Low-Voltage, Double-Edge-Triggered Flip Flop.
PATMOS 2003: 11-20 |