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| 2005 | ||
|---|---|---|
| 9 | P. Chowdhury, C. Chakrabarti: Static task-scheduling algorithms for battery-powered DVS systems. IEEE Trans. VLSI Syst. 13(2): 226-237 (2005) | |
| 2004 | ||
| 8 | J. Kaza, C. Chakrabarti: Design and implementation of low-energy turbo decoders. IEEE Trans. VLSI Syst. 12(9): 968-977 (2004) | |
| 2002 | ||
| 7 | S. H. Tadas, C. Chakrabarti: Architectural approaches to reduce leakage energy in caches. ISCAS (1) 2002: 481-484 | |
| 6 | A. Manzak, C. Chakrabarti: A low power scheduling scheme with resources operating at multiple voltages. IEEE Trans. VLSI Syst. 10(1): 6-14 (2002) | |
| 1999 | ||
| 5 | C. Chakrabarti, D. Gaitonde: Instruction level power model of microcontrollers. ISCAS (1) 1999: 76-79 | |
| 4 | C. Chakrabarti: A DWT-based encoder architecture for symmetrically extended images. ISCAS (4) 1999: 123-126 | |
| 3 | C. Chakrabarti, C. Mumford: Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform. IEEE Trans. VLSI Syst. 7(3): 289-298 (1999) | |
| 1994 | ||
| 2 | C. Chakrabarti: High sample rate array architectures for median filters. IEEE Transactions on Signal Processing 42(3): 707-712 (1994) | |
| 1 | C. Chakrabarti: A comment on `on prime factor mapping for the discrete Hartley transform'. IEEE Transactions on Signal Processing 42(6): 1551-1552 (1994) | |
| 1 | P. Chowdhury | [9] |
| 2 | D. Gaitonde | [5] |
| 3 | J. Kaza | [8] |
| 4 | A. Manzak | [6] |
| 5 | C. Mumford | [3] |
| 6 | S. H. Tadas | [7] |
Colors in the list of coauthors
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