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| 2011 | ||
|---|---|---|
| 40 | Daewoong Kim, Kilhyung Cha, Doo-Seung Hong, Soonwoo Choi, Soo-Ik Chae: A Programmable Video Platform and Its Application Mapping Framework Using the Target Application's SystemC Models. EURASIP J. Emb. Sys. 2011: (2011) | |
| 2010 | ||
| 39 | Soonwoo Choi, Jason J. K. Park, Moonmo Koo, Daewoong Kim, Soo-Ik Chae: A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor. SoCC 2010: 105-108 | |
| 2009 | ||
| 38 | Daewoong Kim, Kilhyung Cha, Soonwoo Choi, Soo-Ik Chae: Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks. SiPS 2009: 173-178 | |
| 37 | Jinhyun Cho, Doowon Lee, Sang-yong Yoon, Sanggyu Park, Soo-Ik Chae: VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications. IEICE Transactions 92-A(1): 279-290 (2009) | |
| 36 | Daewoong Kim, Kilhyung Cha, Soo-Ik Chae: Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator. IEICE Transactions 92-D(7): 1500-1502 (2009) | |
| 35 | Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Katalin Popovici, Xavier Guerin, Ahmed Amine Jerraya, Kai Huang, Lei Li, Xiaolang Yan: Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation. Integration 42(2): 227-245 (2009) | |
| 34 | Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae: A mixed-level virtual prototyping environment for SystemC-based design methodology. Microelectronics Journal 40(7): 1082-1093 (2009) | |
| 2008 | ||
| 33 | Jinhyun Cho, Soonwoo Choi, Soo-Ik Chae: RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow. FDL 2008: 251-252 | |
| 32 | Sang-yong Yoon, Soo-Ik Chae: Cache Optimization for H.264/AVC Motion Compensation. IEICE Transactions 91-D(12): 2902-2905 (2008) | |
| 2007 | ||
| 31 | Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya: Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. DAC 2007: 39-42 | |
| 30 | Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya: Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. SCOPES 2007: 81-89 | |
| 29 | Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Ricardo Reis, Xavier Guerin, Ahmed Amine Jerraya: Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC. Design Autom. for Emb. Sys. 11(4): 249-283 (2007) | |
| 2006 | ||
| 28 | Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae: Reusable component IP design using refinement-based design environment. ASP-DAC 2006: 588-593 | |
| 27 | Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya: Functional modeling techniques for efficient SW code generation of video codec applications. ASP-DAC 2006: 935-940 | |
| 26 | Ren Huang, Soo-Ik Chae: Implementation of an OpenVG Rasterizer with Configurable Anti-Aliasing and Multi-Window Scissoring. CIT 2006: 179 | |
| 25 | Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya: Buffer memory optimization for video codec application modeled in Simulink. DAC 2006: 689-694 | |
| 24 | Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae: A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment. IEEE International Workshop on Rapid System Prototyping 2006: 63-68 | |
| 23 | Seokkee Kim, Soo-Ik Chae: A Bootstrapped Switch for nMOS Reversible Energy Recovery Logic for Low-Voltage Applications. IEICE Transactions 89-C(5): 649-652 (2006) | |
| 2005 | ||
| 22 | Minho Kim, Ingu Hwang, Soo-Ik Chae: A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. ASP-DAC 2005: 631-634 | |
| 21 | Seokkee Kim, Soo-Ik Chae: Implementation of a simple 8-bit microprocessor with reversible energy recovery logic. Conf. Computing Frontiers 2005: 421-426 | |
| 20 | Sanggyu Park, Soo-Ik Chae: A C/C++-Based Functional Verification Framework Using the SystemC Verification Library. IEEE International Workshop on Rapid System Prototyping 2005: 237-239 | |
| 19 | Seokkee Kim, Soo-Ik Chae: Complexity reduction in an nRERL microprocessor. ISLPED 2005: 180-185 | |
| 18 | Sanggyu Park, Soo-Ik Chae: A Two-Week Program for a Platform-Based SoC Design. MSE 2005: 43-44 | |
| 2004 | ||
| 17 | Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya: An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. DAC 2004: 250-255 | |
| 16 | Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae: A Cycle-Accurate Energy Estimator for CMOS Digital Circuits. PATMOS 2004: 159-168 | |
| 2003 | ||
| 15 | Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, Soo-Ik Chae: An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. Design Autom. for Emb. Sys. 8(2-3): 119-138 (2003) | |
| 2001 | ||
| 14 | Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae: An 8-b nRERL microprocessor for ultra-low-energy applications. ASP-DAC 2001: 27-28 | |
| 13 | Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi: Partial bus-invert coding for power optimization of application-specific systems. IEEE Trans. VLSI Syst. 9(2): 377-383 (2001) | |
| 2000 | ||
| 12 | Joonho Lim, Dong-G. Kim, Sang-C. Kang, Soo-Ik Chae: An 8×8 nRERL serial multiplier for ultra-low-power aplications. ASP-DAC 2000: 35-36 | |
| 11 | Kyung-soo Oh, Sang-yong Yoon, Soo-Ik Chae: Emulator Environment Based on an FPGA Prototyping Board. IEEE International Workshop on Rapid System Prototyping 2000: 72-77 | |
| 10 | Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae: A three-port nRERL register file for ultra-low-energy applications. ISLPED 2000: 161-166 | |
| 9 | Koichi Nose, Soo-Ik Chae, Takayasu Sakurai: Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED 2000: 228-230 | |
| 1998 | ||
| 8 | Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi: Partial bus-invert coding for power optimization of system level bus. ISLPED 1998: 127-129 | |
| 7 | Eel-Wan Lee, Soo-Ik Chae: Fast Design of Reduced-Complexity Nearest-Neighbor Classifiers Using Triangular Inequality. IEEE Trans. Pattern Anal. Mach. Intell. 20(5): 562-566 (1998) | |
| 1995 | ||
| 6 | Kyungmin Na, Bumki Jeon, Dong-Il Chang, Soo-Ik Chae, Souguil Ann: Discriminative training of hidden Markov models using overall risk criterion and reduced gradient method. EUROSPEECH 1995 | |
| 5 | Kyungmin Na, Jekwan Ryu, Dong-Il Chang, Soo-Ik Chae, Souguil Ann: Recurrent neural prediction models for speech recognition. EUROSPEECH 1995 | |
| 1994 | ||
| 4 | Sungjun Park, Seung-Jai Min, Soo-Ik Chae: Stereo Correspondence with Discrete-Time Cellular Neural Networks. ISCAS 1994: 225-228 | |
| 3 | Joonho Lim, Eel-Wan Lee, Soo-Ik Chae: Character Recognition by Neural Networks with Single-Layer Training and Rejection Mechanism. ISCAS 1994: 327-330 | |
| 2 | Seung-Jai Min, Eel-Wan Lee, Soo-Ik Chae: A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses. ISCAS 1994: 471-474 | |
| 1993 | ||
| 1 | Eel-Wan Lee, Jae-Hee Won, Soo-Ik Chae: Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm. ISCAS 1993: 1897-1900 | |
Colors in the list of coauthors
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