 | 2011 |
| 22 |  | Shuli Gao,
Dhamin Al-Khalili,
Noureddine Chabini:
Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs.
ICECS 2011: 137-140 |
| 21 |  | Shuli Gao,
Dhamin Al-Khalili,
Noureddine Chabini:
Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs.
IPDPS Workshops 2011: 271-277 |
| 20 |  | Noureddine Chabini,
Marilyn Wolf:
Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus.
IET Computers & Digital Techniques 5(5): 386-392 (2011) |
| 2010 |
| 19 |  | Shuli Gao,
Noureddine Chabini,
Dhamin Al-Khalili,
J. M. Pierre Langlois:
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers.
Signal Processing Systems 58(1): 3-15 (2010) |
| 2009 |
| 18 |  | Shuli Gao,
Dhamin Al-Khalili,
Noureddine Chabini:
Two level decomposition based matrix multiplication for FPGAs.
ICECS 2009: 427-430 |
| 17 |  | Shuli Gao,
Dhamin Al-Khalili,
Noureddine Chabini:
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs.
Int. J. Reconfig. Comp. 2009: (2009) |
| 2007 |
| 16 |  | Shuli Gao,
Noureddine Chabini,
Dhamin Al-Khalili,
J. M. Pierre Langlois:
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers.
ASAP 2007: 18-23 |
| 15 |  | Noureddine Chabini,
Wayne Wolf:
Register binding guided by the size of variables.
ICCD 2007: 587-594 |
| 14 |  | Noureddine Chabini,
Wayne Wolf:
Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints.
IESS 2007: 255-268 |
| 13 |  | Noureddine Chabini:
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs.
PATMOS 2007: 64-74 |
| 12 |  | Shuli Gao,
Noureddine Chabini,
Dhamin Al-Khalili,
J. M. Pierre Langlois:
Optimised realisations of large integer multipliers and squarers using embedded blocks.
IET Computers & Digital Techniques 1(1): 9-16 (2007) |
| 2006 |
| 11 |  | Shuli Gao,
Noureddine Chabini,
Dhamin Al-Khalili,
J. M. Pierre Langlois:
An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers.
AICCSA 2006: 248-254 |
| 2005 |
| 10 |  | Noureddine Chabini,
El Mostapha Aboulhamid,
Ismaïl Chabini,
Yvon Savaria:
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.
ACM Trans. Design Autom. Electr. Syst. 10(2): 187-204 (2005) |
| 9 |  | Noureddine Chabini,
Wayne Wolf:
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints.
IEEE Trans. VLSI Syst. 13(10): 1113-1126 (2005) |
| 2004 |
| 8 |  | Noureddine Chabini,
Wayne Wolf:
An approach for reducing dynamic power consumption in synchronous sequential digital designs.
ASP-DAC 2004: 198-204 |
| 7 |  | Noureddine Chabini,
Wayne Wolf:
An approach for integrating basic retiming and software pipelining.
EMSOFT 2004: 287-296 |
| 6 |  | Noureddine Chabini,
Wayne Wolf:
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.
IEEE Trans. VLSI Syst. 12(6): 573-589 (2004) |
| 2003 |
| 5 |  | Noureddine Chabini,
Ismaïl Chabini,
El Mostapha Aboulhamid,
Yvon Savaria:
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.
ACM Great Lakes Symposium on VLSI 2003: 221-224 |
| 4 |  | Noureddine Chabini,
Wayne Wolf:
Minimizing Variables' Lifetime in Loop-Intensive Applications.
EMSOFT 2003: 100-116 |
| 3 |  | Noureddine Chabini,
Ismaïl Chabini,
El Mostapha Aboulhamid,
Yvon Savaria:
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 346-351 (2003) |
| 2001 |
| 2 |  | Noureddine Chabini,
El Mostapha Aboulhamid,
Yvon Savaria:
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages.
ICCD 2001: 546-552 |
| 1 |  | Noureddine Chabini,
Yvon Savaria:
Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques.
ISSS 2001: 209-214 |