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Francisco J. Cazorla-Almeida
List of publications from the DBLP Bibliography Server - FAQ
| 2012 | ||
|---|---|---|
| 57 | Petar Radojkovic, Vladimir Cakarevic, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero: Optimal task assignment in multithreaded processors: a statistical approach. ASPLOS 2012: 235-248 | |
| 56 | Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero: CPU Accounting for Multicore Processors. IEEE Trans. Computers 61(2): 251-264 (2012) | |
| 55 | Petar Radojkovic, Sylvain Girbal, Arnaud Grasset, Eduardo Quiñones, Sami Yehia, Francisco J. Cazorla: On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments. TACO 8(4): 34 (2012) | |
| 2011 | ||
| 54 | Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero: Hybrid high-performance low-power and ultra-low energy reliable caches. Conf. Computing Frontiers 2011: 12 | |
| 53 | Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero: RVC: a mechanism for time-analyzable real-time processors with faulty caches. HiPEAC 2011: 97-106 | |
| 52 | Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Robert I. Davis, Mateo Valero: IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2011: 280-290 | |
| 51 | Jaume Abella, Francisco J. Cazorla, Eduardo Quiñones, Arnaud Grasset, Sami Yehia, Philippe Bonnot, Dimitris Gizopoulos, Riccardo Mariani, Guillem Bernat: Towards improved survivability in safety-critical systems. IOLTS 2011: 240-245 | |
| 50 | Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides: RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 2011: 25-30 | |
| 49 | Alessandro Morari, Roberto Gioiosa, Robert W. Wisniewski, Francisco J. Cazorla, Mateo Valero: A Quantitative Analysis of OS Noise. IPDPS 2011: 852-863 | |
| 48 | Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Julian Wolf, Theo Ungerer, Sascha Uhrig, Zlatko Petrov: A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks. ISORC 2011: 233-240 | |
| 47 | Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero: Energy-Aware Accounting and Billing in Large-Scale Computing Facilities. IEEE Micro 31(3): 60-71 (2011) | |
| 46 | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Dynamic Cache Partitioning Based on the MLP of Cache Misses. T. HiPEAC 3: 3-23 (2011) | |
| 2010 | ||
| 45 | Michael Beigl, Francisco J. Cazorla-Almeida: ARCS '10 - 23th International Conference on Architecture of Computing Systens 2010, Workshop Proceedings, February 22-23, 2010, Hannover, Germany VDE Verlag 2010 | |
| 44 | Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero: Load balancing using dynamic cache allocation. Conf. Computing Frontiers 2010: 153-164 | |
| 43 | Kamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero: Adapting cache partitioning algorithms to pseudo-LRU replacement policies. IPDPS 2010: 1-12 | |
| 42 | Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose: Power and thermal characterization of POWER6 system. PACT 2010: 7-18 | |
| 41 | Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero: Thread to strand binding of parallel network applications in massive multi-threaded systems. PPOPP 2010: 191-202 | |
| 40 | Victor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero: Trends and techniques for energy efficient architectures. VLSI-SoC 2010: 276-279 | |
| 39 | Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Cassé, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jörg Mische: Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. IEEE Micro 30(5): 66-75 (2010) | |
| 38 | Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero: On the Problem of Evaluating the Performance of Multiprogrammed Workloads. IEEE Trans. Computers 59(12): 1722-1728 (2010) | |
| 2009 | ||
| 37 | Eduardo Quiñones, Emery D. Berger, Guillem Bernat, Francisco J. Cazorla: Using Randomized Caches in Probabilistic Real-Time Systems. ECRTS 2009: 129-138 | |
| 36 | Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero: Hardware support for WCET analysis of hard real-time multicore systems. ISCA 2009: 57-68 | |
| 35 | Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero: Characterizing the resource-sharing levels in the UltraSPARC T2 processor. MICRO 2009: 481-492 | |
| 34 | Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero: ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. PACT 2009: 203-213 | |
| 33 | Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Thread to Core Assignment in SMT On-Chip Multiprocessors. SBAC-PAD 2009: 67-74 | |
| 32 | Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero: CPU Accounting in CMP Processors. Computer Architecture Letters 8(1): 17-20 (2009) | |
| 31 | Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero: An Analyzable Memory Controller for Hard Real-Time CMPs. Embedded Systems Letters 1(4): 86-90 (2009) | |
| 30 | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero: FlexDCP: a QoS framework for CMP architectures. Operating Systems Review 43(2): 86-96 (2009) | |
| 2008 | ||
| 29 | Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero: Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. ARCS 2008: 173-187 | |
| 28 | Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luís Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee: Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. EvoWorkshops 2008: 175-183 | |
| 27 | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MLP-Aware Dynamic Cache Partitioning. HiPEAC 2008: 337-352 | |
| 26 | Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. ICPP 2008: 173-181 | |
| 25 | Pedro A. Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luís Jiménez Laredo, Sally A. McKee: Evolutionary system for prediction and optimization of hardware architecture performance. IEEE Congress on Evolutionary Computation 2008: 1941-1948 | |
| 24 | Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero: Balancing HPC applications through smart allocation of resources in MT processors. IPDPS 2008: 1-12 | |
| 23 | Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero: A Two-Level Load/Store Queue Based on Execution Locality. ISCA 2008: 25-36 | |
| 22 | Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero: Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008: 415-426 | |
| 21 | Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero: Measuring Operating System Overhead on CMT Processors. SBAC-PAD 2008: 133-140 | |
| 20 | Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero: Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD 2008: 63-70 | |
| 19 | Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero: A dynamic scheduler for balancing HPC applications. SC 2008: 41 | |
| 18 | Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith: Multicore Resource Management. IEEE Micro 28(3): 6-16 (2008) | |
| 2007 | ||
| 17 | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Online Prediction of Applications Cache Utility. ICSAMOS 2007: 169-177 | |
| 16 | Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero: On the Problem of Minimizing Workload Execution Time in SMT Processors. ICSAMOS 2007: 66-73 | |
| 15 | Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero: A Flexible Heterogeneous Multi-Core Architecture. PACT 2007: 13-24 | |
| 14 | Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero: FAME: FAirly MEasuring Multithreaded Architectures. PACT 2007: 305-316 | |
| 13 | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MLP-Aware Dynamic Cache Partitioning. PACT 2007: 418 | |
| 12 | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Explaining Dynamic Cache Partitioning Speed Ups. Computer Architecture Letters 6(1): 1-4 (2007) | |
| 2006 | ||
| 11 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Predictable Performance in SMT Processors: Synergy between the OS and SMTs. IEEE Trans. Computers 55(7): 785-799 (2006) | |
| 2005 | ||
| 10 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Architectural support for real-time task scheduling in SMT processors. CASES 2005: 166-176 | |
| 9 | Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero: Kilo-Instruction Processors: Overcoming the Memory Wall. IEEE Micro 25(3): 48-57 (2005) | |
| 2004 | ||
| 8 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Predictable performance in SMT processors. Conf. Computing Frontiers 2004: 433-443 | |
| 7 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Implicit vs. Explicit Resource Allocation in SMT Processors. DSD 2004: 44-51 | |
| 6 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Feasibility of QoS for SMT. Euro-Par 2004: 535-540 | |
| 5 | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. IPDPS 2004 | |
| 4 | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: Dynamically Controlled Resource Allocation in SMT Processors. MICRO 2004: 171-182 | |
| 3 | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández: QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24(4): 24-31 (2004) | |
| 2 | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: Optimising long-latency-load-aware fetch policies for SMT processors. IJHPCN 2(1): 45-54 (2004) | |
| 2003 | ||
| 1 | Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero: Improving Memory Latency Aware Fetch Policies for SMT Processors. ISHPC 2003: 70-85 | |
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