 | 2009 |
|---|
| 10 |       | Daniele Rossi,
José Manuel Cazeaux,
Martin Omaña,
Cecilia Metra,
Abhijit Chatterjee:
Accurate Linear Model for SET Critical Charge Estimation.
IEEE Trans. VLSI Syst. 17(8): 1161-1166 (2009) |
| 2006 |
|---|
| 9 | | Martin Omaña,
José Manuel Cazeaux,
Daniele Rossi,
Cecilia Metra:
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.
DATE 2006: 170-175 |
| 8 |  | Cecilia Metra,
Daniele Rossi,
Martin Omaña,
José Manuel Cazeaux,
T. M. Mak:
Can Clock Faults be Detected Through Functional Test?
DDECS 2006: 168-173 |
| 7 | | Cecilia Metra,
Martin Omaña,
Daniele Rossi,
José Manuel Cazeaux,
T. M. Mak:
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.
IOLTS 2006: 17-22 |
| 2005 |
|---|
| 6 | | Cecilia Metra,
Martin Omaña,
Daniele Rossi,
José Manuel Cazeaux,
T. M. Mak:
The Other Side of the Timing Equation: a Result of Clock Faults.
DFT 2005: 169-177 |
| 5 | | José Manuel Cazeaux,
Daniele Rossi,
Martin Omaña,
Cecilia Metra,
Abhijit Chatterjee:
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.
IOLTS 2005: 23-28 |
| 4 | | José Manuel Cazeaux,
Martin Omaña,
Cecilia Metra:
Novel on-chip circuit for jitter testing in high-speed PLLs.
IEEE T. Instrumentation and Measurement 54(5): 1779-1788 (2005) |
| 3 | | José Manuel Cazeaux,
Daniele Rossi,
Cecilia Metra:
Self-Checking Voter for High Speed TMR Systems.
J. Electronic Testing 21(4): 377-389 (2005) |
| 2004 |
|---|
| 2 | | José Manuel Cazeaux,
Martin Omaña,
Cecilia Metra:
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.
IOLTS 2004: 17-24 |
| 1 | | José Manuel Cazeaux,
Daniele Rossi,
Cecilia Metra:
New High Speed CMOS Self-Checking Voter.
IOLTS 2004: 58-66 |
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