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| 2012 | ||
|---|---|---|
| 78 | Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang: Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012 ACM 2012 | |
| 77 | Yang Sun, Joseph R. Cavallaro: Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture. IEEE Transactions on Signal Processing 60(5): 2617-2627 (2012) | |
| 76 | Predrag Radosavljevic, Kyeong Jin Kim, Hao Shen, Joseph R. Cavallaro: Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems. IEEE Transactions on Signal Processing 60(6): 3240-3252 (2012) | |
| 2011 | ||
| 75 | Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca: 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 IEEE 2011 | |
| 74 | Guohui Wang, Yang Sun, Joseph R. Cavallaro, Yuanbin Guo: High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder. ASAP 2011: 113-121 | |
| 73 | Yang Sun, Guohui Wang, Joseph R. Cavallaro: Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes. ISCAS 2011: 1776-1779 | |
| 72 | Markus Myllylä, Joseph R. Cavallaro, Markku J. Juntti: Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm. IEEE Trans. VLSI Syst. 19(5): 895-899 (2011) | |
| 71 | Kiarash Amiri, Michael Wu, Joseph R. Cavallaro, Jorma Lilleberg: Cooperative Partial Detection Using MIMO Relays. IEEE Transactions on Signal Processing 59(10): 5039-5049 (2011) | |
| 70 | Yang Sun, Joseph R. Cavallaro: Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder. Integration 44(4): 305-315 (2011) | |
| 69 | Kiarash Amiri, Joseph R. Cavallaro, Chris Dick, Raghu Mysore Rao: A High Throughput Configurable SDR Detector for Multi-user MIMO Wireless Systems. Signal Processing Systems 62(2): 233-245 (2011) | |
| 68 | Yang Sun, Joseph R. Cavallaro: A Flexible LDPC/Turbo Decoder Architecture. Signal Processing Systems 64(1): 1-16 (2011) | |
| 67 | Michael Wu, Yang Sun, Siddharth Gupta, Joseph R. Cavallaro: Implementation of a High Throughput Soft MIMO Detector on GPU. Signal Processing Systems 64(1): 123-136 (2011) | |
| 66 | Michael Wu, Yang Sun, Guohui Wang, Joseph R. Cavallaro: Implementation of a High Throughput 3GPP Turbo Decoder on GPU. Signal Processing Systems 65(2): 171-183 (2011) | |
| 2010 | ||
| 65 | Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro: Programming high performance signal processing systems in high level languages. FPGA 2010: 145 | |
| 64 | Yang Sun, Joseph R. Cavallaro: Low-complexity and high-performance soft MIMO detection based on distributed M-algorithm through trellis-diagram. ICASSP 2010: 3398-3401 | |
| 63 | Kiarash Amiri, Michael Wu, Melissa Duarte, Joseph R. Cavallaro: Physical layer algorithm and hardware verification of MIMO relays using cooperative partial detection. ICASSP 2010: 5614-5617 | |
| 62 | Johanna Ketonen, Markku J. Juntti, Joseph R. Cavallaro: Performance: complexity comparison of receivers for a LTE MIMO-OFDM system. IEEE Transactions on Signal Processing 58(6): 3360-3372 (2010) | |
| 61 | Markus Myllylä, Markku J. Juntti, Joseph R. Cavallaro: Implementation aspects of list sphere decoder algorithms for MIMO-OFDM systems. Signal Processing 90(10): 2863-2876 (2010) | |
| 2009 | ||
| 60 | Yang Sun, Joseph R. Cavallaro: High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm. ACM Great Lakes Symposium on VLSI 2009: 445-450 | |
| 59 | Kiarash Amiri, Joseph R. Cavallaro: Partial detection for multiple antenna cooperation. CISS 2009: 669-674 | |
| 58 | Markus Myllylä, Markku J. Juntti, Joseph R. Cavallaro: Architecture design and implementation of the increasing radius - List sphere detector algorithm. ICASSP 2009: 553-556 | |
| 57 | Michael Wu, Siddharth Gupta, Yang Sun, Joseph R. Cavallaro: A GPU implementation of a real-time MIMO detector. SiPS 2009: 303-308 | |
| 56 | Yang Sun, Joseph R. Cavallaro, Tai Ly: Scalable and low power LDPC decoder design using high level algorithmic synthesis. SoCC 2009: 267-270 | |
| 55 | Predrag Radosavljevic, Yuanbin Guo, Joseph R. Cavallaro: Probabilistically bounded soft sphere detection for MIMO-OFDM receivers: algorithm and system architecture. IEEE Journal on Selected Areas in Communications 27(8): 1318-1330 (2009) | |
| 2008 | ||
| 54 | Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Cavallaro: Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. ASAP 2008: 209-214 | |
| 53 | Kiarash Amiri, Davood Shamsi, Behnaam Aazhang, Joseph R. Cavallaro: Adaptive codebook for beamforming in limited feedback MIMO systems. CISS 2008: 994-998 | |
| 52 | Predrag Radosavljevic, Kyeong Jin Kim, Joseph R. Cavallaro: QRD-QLD Searching Based Sphere Detection for Emerging MIMO Downlink OFDM Receivers. GLOBECOM 2008: 4212-4216 | |
| 51 | Kiarash Amiri, Chris Dick, Raghu Mysore Rao, Joseph R. Cavallaro: Novel Sort-Free Detector with Modified Real-Valued Decomposition (M-RVD) Ordering in MIMO Systems. GLOBECOM 2008: 4217-4221 | |
| 50 | Predrag Radosavljevic, Joseph R. Cavallaro: Design of block-structured LDPC codes for iterative receivers with soft sphere detection. ICASSP 2008: 2693-2696 | |
| 49 | Yang Sun, Joseph R. Cavallaro: Unified decoder architecture for LDPC/turbo codes. SiPS 2008: 13-18 | |
| 48 | Yang Sun, Joseph R. Cavallaro: A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards. SoCC 2008: 367-370 | |
| 47 | Marjan Karkooti, Joseph R. Cavallaro: Cooperative Communications Using Scalable, Medium Block-length LDPC Codes. WCNC 2008: 88-93 | |
| 46 | Sridhar Rajagopal, Joseph R. Cavallaro: Communication Processors for Wireless Systems. Wiley Encyclopedia of Computer Science and Engineering 2008 | |
| 45 | Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro: Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. IJES 3(3): 128-140 (2008) | |
| 44 | Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro: Configurable LDPC Decoder Architectures for Regular and Irregular Codes. Signal Processing Systems 53(1-2): 73-88 (2008) | |
| 2007 | ||
| 43 | Markus Myllylä, Markku J. Juntti, Joseph R. Cavallaro: Implementation Aspects of List Sphere Detector Algorithms. GLOBECOM 2007: 3915-3920 | |
| 42 | Yang Sun, Marjan Karkooti, Joseph R. Cavallaro: VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes. ISCAS 2007: 2104-2107 | |
| 41 | Joseph R. Cavallaro, Sanjay Rajopadhye, Lothar Thiele, Tobias Noll: Special Issue on ASAP 2004 Conference. VLSI Signal Processing 49(1): 1-2 (2007) | |
| 2006 | ||
| 40 | Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro: Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation. ASAP 2006: 360-367 | |
| 39 | Markus Myllylä, Pirkka Silvola, Markku J. Juntti, Joseph R. Cavallaro: Comparison of Two Novel List Sphere Detector Algorithms for MIMO-OFDM Systems. PIMRC 2006: 1-5 | |
| 38 | Predrag Radosavljevic, Alexandre de Baynast, Marjan Karkooti, Joseph R. Cavallaro: Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area. PIMRC 2006: 1-5 | |
| 37 | Yuanbin Guo, Jianzhong (Charlie) Zhang, Dennis McCain, Joseph R. Cavallaro: An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture. EURASIP J. Adv. Sig. Proc. 2006: (2006) | |
| 36 | Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro, Andres Takach: Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology. EURASIP J. Emb. Sys. 2006: (2006) | |
| 35 | Sridhar Rajagopal, Joseph R. Cavallaro: Truncated Online Arithmetic with Applications to Communication Systems. IEEE Trans. Computers 55(10): 1240-12529 (2006) | |
| 34 | Panagiotis Demestichas, Guillaume Vivier, Joseph R. Cavallaro: Special Issue on Reconfigurable Radio Technologies in Support of Ubiquitous Seamless Computing. MONET 11(6): 775-777 (2006) | |
| 33 | Yuanbin Guo, Joseph R. Cavallaro: A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems. VLSI Signal Processing 44(3): 195-217 (2006) | |
| 2005 | ||
| 32 | Manik Gadhiok, Ricky Hardy, Patrick Murphy, J. Patrick Frantz, Hyeokho Choi, Joseph R. Cavallaro: An FPGA-Based Daughtercard for TI's C6000 family of DSKs. MSE 2005: 85-86 | |
| 31 | S. Das, Elza Erkip, Joseph R. Cavallaro, Behnaam Aazhang: Low-complexity iterative multiuser detection and decoding for real-time applications. IEEE Transactions on Wireless Communications 4(4): 1455-1460 (2005) | |
| 2004 | ||
| 30 | Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro: Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems. ISCAS (4) 2004: 77-80 | |
| 29 | Marjan Karkooti, Joseph R. Cavallaro: Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding. ITCC (1) 2004: 579-585 | |
| 28 | Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner: Design Space Exploration for Real-Time Embedded Stream Processors. IEEE Micro 24(4): 54-66 (2004) | |
| 2003 | ||
| 27 | Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro: Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. ASAP 2003: 260-270 | |
| 26 | Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cavallaro: Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA. IEEE International Workshop on Rapid System Prototyping 2003: 179-185 | |
| 25 | Patrick Murphy, J. Patrick Frantz, Erik Welsh, Ricky Hardy, Tinoosh Mohsenin, Joseph R. Cavallaro: VALID: Custom ASIC Verification and FPGA Education Platform. MSE 2003: 64-65 | |
| 24 | Bryan A. Jones, Joseph R. Cavallaro: A Rapid Prototyping Environment for Wireless Communication Embedded Systems. EURASIP J. Adv. Sig. Proc. 2003(6): 603-614 (2003) | |
| 2002 | ||
| 23 | Martin L. Leuschen, Joseph R. Cavallaro, Ian D. Walker: Robotic Fault Detection using Nonlinear Analytical Redundancy. ICRA 2002: 456-463 | |
| 22 | Yuanbin Guo, Joseph R. Cavallaro: Post-compensation of RF non-linearity in mobile OFDM systems by estimation of memory-less polynomial. ISCAS (1) 2002: 217-220 | |
| 21 | Frank Livingston, Vikram Chandrasekhar, M. Vaya, Joseph R. Cavallaro: Handset detector architectures for DS-CDMA wireless systems. ISCAS (3) 2002: 265-268 | |
| 20 | Yuanbin Guo, Joseph R. Cavallaro: A novel adaptive pre-distorter using LS estimation of SSPA non-linearity in mobile OFDM systems. ISCAS (3) 2002: 453-456 | |
| 19 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang: Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers. IEEE Transactions on Wireless Communications 1(3): 468-479 (2002) | |
| 18 | Gang Xu, Sridhar Rajagopal, Joseph R. Cavallaro, Behnaam Aazhang: VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers. VLSI Signal Processing 30(1-3): 21-33 (2002) | |
| 17 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang: Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers. VLSI Signal Processing 31(2): 143-156 (2002) | |
| 2001 | ||
| 16 | Sridhar Rajagopal, Joseph R. Cavallaro: On-line Arithmetic for Detection in Digital Communication Receivers. IEEE Symposium on Computer Arithmetic 2001: 257-265 | |
| 15 | Sridhar Rajagopal, Joseph R. Cavallaro: A bit-streaming, pipelined multiuser detector for wireless communication receivers. ISCAS (4) 2001: 128-131 | |
| 14 | Chaitali Sengupta, Joseph R. Cavallaro, Behnaam Aazhang: On multipath channel estimation for CDMA systems using multiple sensors. IEEE Transactions on Communications 49(3): 543-553 (2001) | |
| 2000 | ||
| 13 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang: Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. ASAP 2000: 173-184 | |
| 1999 | ||
| 12 | Ian D. Walker, Joseph R. Cavallaro, Martin L. Leuschen: Keeping the Analog Genie in the Bottle: A Case for Digital Robots. ICRA 1999: 1063-1070 | |
| 1997 | ||
| 11 | B. Haller, J. Goetze, Joseph R. Cavallaro: Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering. ASAP 1997: 162- | |
| 1994 | ||
| 10 | M. L. Visinsky, Ian D. Walker, Joseph R. Cavallaro: New Dynamic Model-Based Fault Detection Thresholds for Robot Manipulators. ICRA 1994: 1388-1395 | |
| 9 | Nariankadu D. Hemkumar, Joseph R. Cavallaro: Redundant and On-Line CORDIC for Unitary Transformations. IEEE Trans. Computers 43(8): 941-954 (1994) | |
| 8 | Ian D. Walker, Joseph R. Cavallaro: Parallel VLSI architectures for real-time kinematics of redundant robots. Journal of Intelligent and Robotic Systems 9(1-2): 25-43 (1994) | |
| 1993 | ||
| 7 | Ian D. Walker, Joseph R. Cavallaro: Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots. ICRA (1) 1993: 870-877 | |
| 6 | M. L. Visinsky, Ian D. Walker, Joseph R. Cavallaro: Layered Dynamic Fault Detection and Tolerance for Robots. ICRA (2) 1993: 180-187 | |
| 5 | Nariankadu D. Hemkumar, Joseph R. Cavallaro: Efficient complex matrix transformations with CORDIC. IEEE Symposium on Computer Arithmetic 1993: 122-129 | |
| 4 | Kishore Kota, Joseph R. Cavallaro: Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors. IEEE Trans. Computers 42(7): 769-779 (1993) | |
| 1991 | ||
| 3 | Arati S. Deo, Joseph R. Cavallaro, Ian D. Walker: New Real-Time Robot Motion Algorithms Using Parallel VLSI Architectures. PPSC 1991: 369-375 | |
| 1988 | ||
| 2 | Joseph R. Cavallaro, Franklin T. Luk: CORDIC Arithmetic for an SVD Processor. J. Parallel Distrib. Comput. 5(3): 271-290 (1988) | |
| 1987 | ||
| 1 | Joseph R. Cavallaro, Franklin T. Luk: CORDIC arithmetic for an SVD processor. IEEE Symposium on Computer Arithmetic 1987: 113-120 | |
Colors in the list of coauthors
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