Mario R. Casu

	2011
30		Mario R. Casu, Stefano Colazzo, Paolo Mantovani: Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study. ACM Great Lakes Symposium on VLSI 2011: 163-168
29		Mario R. Casu: Half-buffer retiming and token cages for synchronous elastic circuits. IET Computers & Digital Techniques 5(4): 318-330 (2011)
28		Mario R. Casu, Massimo Ruo Roch, Sergio Tota, Maurizio Zamboni: A NoC-based hybrid message-passing/shared-memory approach to CMP design. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 261-273 (2011)
	2010
27		Mario R. Casu: Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming. ASYNC 2010: 128-137
26		Massimo Cutrupi, Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano: A flexible UWB Transmitter for breast cancer detection imaging systems. DATE 2010: 1076-1081
25		Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Rostagno, Maurizio Zamboni: MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. DATE 2010: 45-50
	2009
24		Mario R. Casu, Luca Macchiarulo: Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis. Electr. Notes Theor. Comput. Sci. 245: 35-50 (2009)
23		Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni: A Case Study for NoC-Based Homogeneous MPSoC Architectures. IEEE Trans. VLSI Syst. 17(3): 384-388 (2009)
22		Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni: A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design. Integration 42(1): 47-60 (2009)
	2008
21		Mario R. Casu, Marco Crepaldi, Mariagrazia Graziano: A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver. IEEE Trans. on Circuits and Systems 55-I(5): 1368-1381 (2008)
	2007
20		Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni: An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. DATE 2007: 1424-1429
19		Mario R. Casu, Luca Macchiarulo: Adaptive Latency-Insensitive Protocols. IEEE Design & Test of Computers 24(5): 442-452 (2007)
	2006
18		Sergio Tota, Mario R. Casu, Luca Macchiarulo: Implementation analysis of NoC: a MPSoC trace-driven approach. ACM Great Lakes Symposium on VLSI 2006: 204-209
17		Mario R. Casu, Luca Macchiarulo: Floorplanning With Wire Pipelining in Adaptive Communication Channels. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2996-3004 (2006)
	2005
16		Mario R. Casu, Luca Macchiarulo: A New System Design Methodology for Wire Pipelined SoC. DATE 2005: 944-945
15		Mario R. Casu, Luca Macchiarulo: Floorplan assisted data rate enhancement through wire pipelining: a real assessment. ISPD 2005: 121-128
14		Mario R. Casu, Luca Macchiarulo: Throughput-driven floorplanning with wire pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 663-675 (2005)
13		Mario R. Casu, Giuseppe Durisi: Implementation aspects of a transmitted-reference UWB receiver. Wireless Communications and Mobile Computing 5(5): 537-549 (2005)
	2004
12		Mario R. Casu, Luca Macchiarulo: A new approach to latency insensitive design. DAC 2004: 576-581
11		Mario R. Casu, Luca Macchiarulo: Issues in Implementing Latency Insensitive Protocols. DATE 2004: 1390-1391
10		Mario R. Casu, Luca Macchiarulo: On-Chip Transparent Wire Pipelining. ICCD 2004: 160-167
9		Mario R. Casu, Luca Macchiarulo: Floorplanning for throughput. ISPD 2004: 62-69
8		Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. VLSI Syst. 12(4): 349-358 (2004)
7		Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectronics Journal 35(10): 849-857 (2004)
	2003
6		M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS 2003: 121-130
5		Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni: Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS 2003: 90-100
4		Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Coupled electro-thermal modeling and optimization of clock networks. Microelectronics Journal 34(12): 1175-1185 (2003)
	2002
3		Mario R. Casu, Philippe Flatresse: Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. MTDT 2002: 163-167
2		Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni: Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS 2002: 198-208
	2001
1		Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni: Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED 2001: 287-290

Coauthor Index

1	M. Addino	[6]
2	Stefano Colazzo	[30]
3	Marco Crepaldi	[20] [21] [22] [26]
4	Massimo Cutrupi	[26]
5	Giuseppe Durisi	[13]
6	Philippe Flatresse	[3]
7	Mariagrazia Graziano (M. Graziano)	[2] [4] [5] [7] [8] [20] [21] [22] [26]
8	Luca Macchiarulo	[9] [10] [11] [12] [14] [15] [16] [17] [18] [19] [23] [24]
9	Paolo Mantovani	[30]
10	Guido Masera	[1] [2] [4] [5] [6] [7] [8]
11	Gianluca Piccinini	[1] [2] [4] [5] [6] [7] [8]
12	M. M. Prono	[2]
13	Massimo Ruo Roch	[23] [25] [28]
14	Luca Rostagno	[25]
15	Sergio Tota	[18] [23] [25] [28]
16	Maurizio Zamboni	[1] [2] [4] [5] [6] [7] [8] [20] [22] [23] [25] [28]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page