Emmanuel Casseau

	2012
37		Erwan Raffin, Christophe Wolinski, François Charot, Emmanuel Casseau, Antoine Floch, Krzysztof Kuchcinski, Stéphane Chevobbe, Stéphane Guyetant: Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture. IJERTCS 3(1): 1-30 (2012)
36		Emmanuel Casseau, Bertrand Le Gal: Design of multi-mode application-specific cores based on high-level synthesis. Integration 45(1): 9-21 (2012)
35		Chenglong Xiao, Emmanuel Casseau: Exact custom instruction enumeration for extensible processors. Integration 45(3): 263-270 (2012)
	2011
34		Chenglong Xiao, Emmanuel Casseau: An efficient algorithm for custom instruction enumeration. ACM Great Lakes Symposium on VLSI 2011: 187-192
33		Chenglong Xiao, Emmanuel Casseau: Efficient custom instruction enumeration for extensible processors. ASAP 2011: 211-214
32		Chenglong Xiao, Emmanuel Casseau: Efficient maximal convex custom instruction enumeration for extensible processors. DASIP 2011: 137-143
31		Daniel Menard, Hai-Nam Nguyen, François Charot, Stéphane Guyetant, Jérémie Guillot, Erwan Raffin, Emmanuel Casseau: Exploiting reconfigurable SWP operators for multimedia applications. ICASSP 2011: 1717-1720
30		Andrei Banciu, Emmanuel Casseau, Daniel Menard, Thierry Michel: Stochastic modeling for floating-point to fixed-point conversion. SiPS 2011: 180-185
29		Hervé Yviquel, Emmanuel Casseau, Matthieu Wipliez, Mickaël Raulet: Efficient multicore scheduling of dataflow process networks. SiPS 2011: 198-203
28		Bertrand Le Gal, Emmanuel Casseau: Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. EURASIP J. Adv. Sig. Proc. 2011: (2011)
27		Bertrand Le Gal, Emmanuel Casseau: Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. Signal Processing Systems 62(3): 341-357 (2011)
	2010
26		Andrei Banciu, Emmanuel Casseau, Daniel Menard, Thierry Michel: A case study of the stochastic modeling approach for range estimation. DASIP 2010: 128-135
25		Cecile Beaumin, Olivier Sentieys, Emmanuel Casseau, Arnaud Carer: A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. DASIP 2010: 152-159
24		Erwan Raffin, Christophe Wolinski, François Charot, Krzysztof Kuchcinski, Stéphane Guyetant, Stéphane Chevobbe, Emmanuel Casseau: Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture. DASIP 2010: 168-175
23		Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet: High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1736-1749 (2010)
	2009
22		Daniel Menard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David: Reconfigurable Operator Based Multimedia Embedded Processor. ARC 2009: 39-49
21		Shafqat Khan, Emmanuel Casseau, Daniel Menard: Reconfigurable SWP Operator for Multimedia Processing. ASAP 2009: 199-202
20		Emmanuel Casseau, Bertrand Le Gal: High-level synthesis for the design of FPGA-based signal processing systems. ICSAMOS 2009: 25-32
	2008
19		Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet: Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. IEEE Trans. VLSI Syst. 16(11): 1454-1464 (2008)
18		Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina: Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. Technique et Science Informatiques 27(9-10): 1129-1154 (2008)
	2007
17		Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy: Synthesis of Multimode digital signal processing systems. AHS 2007: 318-325
16		Sylvain Huet, Sébastien LeNours, Olivier Pasquier, Emmanuel Casseau: Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications. FDL 2007: 177-184
15		Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin: A design flow dedicated to multi-mode architectures for DSP applications. ICCAD 2007: 604-611
14		Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin: Constrained algorithmic IP design for system-on-chip. Integration 40(2): 94-105 (2007)
	2006
13		Sylvain Huet, Emmanuel Casseau, Olivier Pasquier: A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. DSD 2006: 240-250
12		Sylvain Huet, Emmanuel Casseau, Olivier Pasquier, Sébastien LeNours: Hardware Communication Refinement in Digital Signal Processing. FDL 2006: 177-185
11		Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau: Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. SiPS 2006: 280-285
10		Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin: A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embedded Comput. Syst. 5(1): 29-53 (2006)
9		Guillaume Savaton, Emmanuel Casseau, Eric Martin: Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. Signal Processing 86(7): 1375-1399 (2006)
8		Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin: G729 Voice Decoder Design. VLSI Signal Processing 42(2): 173-184 (2006)
	2005
7		Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno: Hardware Virtual Components Compliant with Communication System Standards. DSD 2005: 88-95
6		Sylvain Huet, Emmanuel Casseau, Olivier Pasquier: Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. IEEE International Workshop on Rapid System Prototyping 2005: 240-243
5		Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin: Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. ISVLSI 2005: 268-269
	2004
4		Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin: Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) 2004: 173-176
3		Emmanuel Casseau, Christophe Jégo, Eric Martin: Synthèse architecturale d'applications temps réel pour technologies submicroniques. Technique et Science Informatiques 23(1): 35-66 (2004)
	1999
2		Christophe Jégo, Emmanuel Casseau, Eric Martin: Architectural Synthesis with Interconnection Cost Control. VLSI 1999: 509-520
	1994
1		Emmanuel Casseau, Dominique Degrugillier: A Linear Systolic Array for LU Decomposition. VLSI Design 1994: 353-358

Coauthor Index

1	Nabil Abdelli	[7]
2	Caaliph Andriamisaina	[11] [15] [17] [18] [23]
3	Mohamed Atri	[8]
4	Adel Baganne	[10] [14]
5	Andrei Banciu	[26] [30]
6	Cecile Beaumin	[25]
7	Pierre Bomel	[7] [10] [14]
8	Arnaud Carer	[25]
9	François Charot	[24] [31] [37]
10	Cyrille Chavet	[15] [23]
11	Stéphane Chevobbe	[22] [24] [37]
12	Philippe Coussy	[10] [14] [15] [17] [23]
13	Raphaël David	[22]
14	Dominique Degrugillier	[1]
15	Antoine Floch	[37]
16	Anne-Marie Fouilliart (Anne-Marie Fouillart)	[7]
17	Bertrand Le Gal	[4] [5] [7] [11] [18] [19] [20] [27] [28] [36]
18	Jérémie Guillot	[31]
19	Stéphane Guyetant	[22] [24] [31] [37]
20	Nathalie Le Heno	[4] [7]
21	Sylvain Huet	[5] [6] [12] [13] [16] [19]
22	Christophe Jégo	[2] [3] [4] [7]
23	Emmanuel Juin	[15]
24	Philippe Kajfasz	[7]
25	Shafqat Khan	[21] [22]
26	Krzysztof Kuchcinski	[24] [37]
27	Sébastien LeNours	[12] [16]
28	Eric Martin	[2] [3] [4] [5] [8] [9] [10] [14] [15]
29	Mehrez Marzougui	[8]
30	Daniel Menard	[21] [22] [26] [30] [31]
31	Thierry Michel	[26] [30]
32	Hai-Nam Nguyen	[31]
33	Olivier Pasquier	[6] [12] [13] [16]
34	Erwan Raffin	[24] [31] [37]
35	Mickaël Raulet	[29]
36	Guillaume Savaton	[9]
37	Fatma Sayadi	[8]
38	Olivier Sentieys	[22] [25]
39	Rached Tourki	[8]
40	Pascal Urard	[15]
41	Matthieu Wipliez	[29]
42	Christophe Wolinski	[24] [37]
43	Chenglong Xiao	[32] [33] [34] [35]
44	Hervé Yviquel	[29]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page