Geert Carchon

	2010
6		Wen-Chieh Wang, Zue-Der Huang, Geert Carchon, Abdelkarim Mercha, Stefaan Decoutere, Walter De Raedt, Chung-Yu Wu: 45-nm Planar bulk-CMOS 23-GHz LNAs with high-Q above-IC inductors. ISCAS 2010: 741-744
	2006
5		J. Balachandran, Steven Brebels, Geert Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne: Analysis and modeling of power grid transmission lines. DATE 2006: 33-38
4		J. Balachandran, Steven Brebels, Geert Carchon, Walter De Raedt, Eric Beyne, Maarten Kuijk, Bart Nauwelaers: Constant Impedance Scaling Paradigm for Scaling LC transmission lines. ISQED 2006: 387-392
3		J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne: Constant impedance scaling paradigm for interconnect synthesis. SLIP 2006: 99-105
2		J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne: Wafer-level package interconnect options. IEEE Trans. VLSI Syst. 14(6): 654-659 (2006)
	2005
1		J. Balachandran, Steven Brebels, Geert Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne: Package level interconnect options. SLIP 2005: 21-27

Coauthor Index

1	J. Balachandran	[1] [2] [3] [4] [5]
2	Eric Beyne	[1] [2] [3] [4] [5]
3	Steven Brebels	[1] [2] [3] [4] [5]
4	Stefaan Decoutere	[6]
5	Zue-Der Huang	[6]
6	Maarten Kuijk	[2] [3] [4]
7	Abdelkarim Mercha	[6]
8	Bart Nauwelaers	[1] [2] [3] [4] [5]
9	Walter De Raedt	[1] [2] [3] [4] [5] [6]
10	Wen-Chieh Wang	[6]
11	T. Webers	[1] [5]
12	Chung-Yu Wu	[6]

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page